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[Othershuzizhong

Description: 用vc实现数字钟的功能,包含工作站,源代码和源程序.-with vc digital bell functions, including workstations, source code and source.
Platform: | Size: 39936 | Author: 闲闲 | Hits:

[SCMdata-shuzizhong

Description: 此文件是本人设计的一个多功能数字钟的详细资料,现供大家参考.-I designed a multi-function digital clock detailed information is available for your reference.
Platform: | Size: 25600 | Author: | Hits:

[Software Engineeringshuzizhong

Description: 本程序可以实现多功能数字钟,非常实用,供大家参考-This procedure can realize multi-function digital clock, very useful for reference
Platform: | Size: 13312 | Author: | Hits:

[assembly languageshuzizhong

Description: 此源代码可以通过对数字钟的加与减来实现数字钟的调整-This source code on the digital clock can increase or decrease the number of minutes to realize the adjustment of
Platform: | Size: 2048 | Author: 刘伟 | Hits:

[Booksshuzizhong

Description: 介绍了用VHDL设计数字钟的相关知识,是学习VHDL的经典例子.-Introduction with VHDL design knowledge digital clock is a classic example of learning VHDL.
Platform: | Size: 31744 | Author: | Hits:

[Software Engineeringshuzizhong

Description: 是基于EDA系统上的一24小时制的数字钟设计,利用EDA系统通过Quartus2直接运行。-EDA system is based on a 24-hour digital clock design, the use of EDA system, through direct Quartus2 run.
Platform: | Size: 190464 | Author: nana | Hits:

[SCMshuzizhong

Description: 电子数字钟的原理分析。有电路图。还含有c源程序-The principle of electronic digital clock analysis. There are circuit diagrams. Also contains c source code
Platform: | Size: 16384 | Author: 郭小华 | Hits:

[assembly languageshuzizhong

Description: 简单使用的数字电路 数字钟,集电路原理图,说明于一体
Platform: | Size: 427008 | Author: hua | Hits:

[Documentsshuzizhong

Description: 数字钟的实验报告,含源代码与原理图和仿真波形
Platform: | Size: 92160 | Author: 晓明 | Hits:

[VHDL-FPGA-Verilogshuzizhong

Description: 数字钟代码,用VHDL语言设计一个数字钟系统,该系统具有显示时、分、秒的功能,具有较时功能,具有整点报时功能。-Digital Clock code using VHDL language to design a digital clock system, which has a display hours, minutes and seconds functions, when a more functional, with the whole point timekeeping function.
Platform: | Size: 1024 | Author: SDFG | Hits:

[SCMshuzizhong-yejing

Description: 自己写的数字电子钟的代码(含液晶),用得到的,下来看看吧。-Write your own digital electronic bell code (including the LCD), used to be, and down to see it.
Platform: | Size: 10240 | Author: 张三 | Hits:

[assembly languageshuzizhong

Description: 开机时,显示12:00:00的时间开始计时; P0.0/AD0控制“秒”的调整,每按一次加1秒; P0.1/AD1控制“分”的调整,每按一次加1分; P0.2/AD2控制“时”的调整,每按一次加1个小时; -Boot-up, indicating the start time 12:00:00 time P0.0/AD0 control seconds of adjustment, every time plus 1 seconds P0.1/AD1 control points of adjustment, every time plus 1 points P0.2/AD2 control when adjustments, every time plus 1 hours
Platform: | Size: 53248 | Author: 张华 | Hits:

[SCMshuzizhong

Description: 我上传的一些单片机的资料,数字钟的实验程序,希望对大家有帮助-I uploaded some Singlechip information, digital clock Experimental procedures, we hope to help
Platform: | Size: 1024 | Author: | Hits:

[Other systemsshuzizhong

Description: 数字钟的解决方案 基于proteus的c代码 希望对你们受用-Digital clock solution is based on the Proteus of the c code you wish to benefit
Platform: | Size: 196608 | Author: luo | Hits:

[assembly languageshuzizhong

Description: 多功能数字钟,带论文,大家分享和指点,希望对大家有帮助,-Multi-function digital clock with papers and advice to share with you, I hope all of you help,
Platform: | Size: 96256 | Author: S__G__J | Hits:

[VHDL-FPGA-Verilogshuzizhong

Description: 设计一个能进行时、分、秒计时的十二小时制或二十四小时制的数字钟,并具有定时与闹钟功能,能在设定的时间发出闹铃音,能非常方便地对小时、分钟和秒进行手动调节以校准时间,每逢整点,产生报时音报时。 实验平台: 1. 一台PC机; 2. MAX+PLUSII10.1。 Verilog HDL语言实现,还有完整的实验报告-The design of a can be hours, minutes, seconds time of 12 hours or 24 hours system, digital clock, and has from time to time with the alarm clock function, can be set to issue a sound alarm can be very convenient to hours, minutes and seconds for manual adjustment to calibrate the time, whenever there is the whole point, resulting in timekeeping timekeeping tone. Experimental platform: 1. A PC machine 2. MAX+ PLUSII10.1. Verilog HDL language, as well as a complete experimental report
Platform: | Size: 425984 | Author: 盼盼 | Hits:

[VHDL-FPGA-Verilogshuzizhong

Description: 可预置数字钟,用VHDL语言编写,LED显示,普通数字钟表。-Digital clock can be preset using VHDL language, LED display, an ordinary digital watch.
Platform: | Size: 1422336 | Author: pj | Hits:

[Education soft systemshuzizhong

Description: 大家都来顶一下啊,这是我自己亲手做的课程设计。我希望大家过来-We all look to the top ah, that I personally do curriculum design. I hope that we come
Platform: | Size: 311296 | Author: lidong | Hits:

[Othershuzizhong

Description: 1.正常走时,能按时钟功能进行小时,分钟,秒计时并显示时间 2.调整时间,校准时间; 3.在简易数字钟基础上,增加整点报时功能; 4.增加定时报闹功能; -1. Normal travel time, according to the clock features hour, minute, second time and display time 2. Adjust the time, calibration time 3. At the basis of simple digital clock, increasing the whole point timekeeping function 4. Times set to increase downtown functions
Platform: | Size: 195584 | Author: 吴佳秋 | Hits:

[SCMshuzizhong

Description: 数字钟 液晶 ds1302 闹钟 秒表 生日提醒-stopwatch
Platform: | Size: 74752 | Author: 张春 | Hits:
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