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Description: 直接将扩展名改为.pas即可使用，是一个关于登录的pas源码。-directly to the extension changed. Pas can use, is a Sign of the pas source.
Platform: |
Size: 1375 |
Author: 李菜功 |
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Description: Files presented:
README.txt - This file. Plaintext documentation of my work.
go - Shell Scripts for running the codes.
cmds - Prolog commands used for executing the codes and generate output.
hexsud.pl - Prolog codes for the 16x16 Sudoku solver.
input - Hex sudoku input file from the hw assignment page.
Because Prolog input is hard to deal with full-stop sign, the input file extension is eliminated.
hexsud - Another testing Hex Sudoku input file.-Files presented : README.txt-This file. Plaintext documentati on of my work. go-Shell Scripts for running the c odes. cmds - Prolog used for executing commands the codes and generate output. hexsud.pl - Prol og codes for the 16x16 Sudoku solver. input-Hex sudoku input file hw assignment from the page. B ecause Prolog input is hard to deal with full-st op sign. the input file extension is eliminated. hexsud - Another testing Hex Sudoku input file.
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Size: 6204 |
Author: emerald |
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Description: This is an extension of sign example. You can design your own traffic sign by using Verilog. And the result from Verilog can be seen by the attached C file.
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Size: 260417 |
Author: Annbb |
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Description: 直接将扩展名改为.pas即可使用，是一个关于登录的pas源码。-directly to the extension changed. Pas can use, is a Sign of the pas source.
Platform: |
Size: 1024 |
Author: 李菜功 |
Hits:
Description: Files presented:
README.txt - This file. Plaintext documentation of my work.
go - Shell Scripts for running the codes.
cmds - Prolog commands used for executing the codes and generate output.
hexsud.pl - Prolog codes for the 16x16 Sudoku solver.
input - Hex sudoku input file from the hw assignment page.
Because Prolog input is hard to deal with full-stop sign, the input file extension is eliminated.
hexsud - Another testing Hex Sudoku input file.-Files presented : README.txt-This file. Plaintext documentati on of my work. go-Shell Scripts for running the c odes. cmds- Prolog used for executing commands the codes and generate output. hexsud.pl- Prol og codes for the 16x16 Sudoku solver. input-Hex sudoku input file hw assignment from the page. B ecause Prolog input is hard to deal with full-st op sign. the input file extension is eliminated. hexsud- Another testing Hex Sudoku input file.
Platform: |
Size: 6144 |
Author: |
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Description: This is an extension of sign example. You can design your own traffic sign by using Verilog. And the result from Verilog can be seen by the attached C file.
Platform: |
Size: 260096 |
Author: Annbb |
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Description: Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift range is 0 to 15.
6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it
shifts input data to left.
7. When the signal SIGN is high, the input data is a signed number and it shifts with
sign extension. However, the input data is an unsigned number if the signal SIGN
is low.
8. You can only use following gates in Table I and need to include the delay
information (Tplh, Tphl) in your design.
Platform: |
Size: 4096 |
Author: hugo |
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Description: Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift range is 0 to 15.
6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it
shifts input data to left.
7. When the signal SIGN is high, the input data is a signed number and it shifts with
sign extension. However, the input data is an unsigned number if the signal SIGN
is low.
8. You can only use following gates in Table I and need to include the delay
information (Tplh, Tphl) in your design.
Platform: |
Size: 6119424 |
Author: hugo |
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Description: 潘明海 刘英哲 于维双 (论文)
中文摘要：
本文讨论了一种可在FPGA上实现的FFT结构。该结构采用基于流水线结构和快速并行乘法器的蝶形处理器。乘法器采用改进的Booth算法，简化了部分积符号扩展，使用Wallace树结构和4-2压缩器对部分积归约。以8点复点FFT为实例设计相应的控制电路。使用VHDL语言完成设计，并综合到FPGA中。从综合的结果看该结构可在XC4025E-2上以52MHz的时钟高速运行。在此基础上易于扩展为大点数FFT运算结构。
-Pan Minghai Liuying Zhe Yu-dimensional pairs (thesis) Chinese Abstract: This paper discusses an FPGA can be implemented on the structure of the FFT. The architecture based on pipeline architecture and fast parallel multiplier butterfly processor. Multiplier using modified Booth algorithm simplifying the partial product sign extension, use the Wallace tree and 4-2 compressor for partial product reduction. 8-point complex-point FFT as an example design of the corresponding control circuit. To complete the design using the VHDL language, and integrated into the FPGA. From the results of a comprehensive look at the structure can be XC4025E-2 with 52MHz clock on the high-speed operation. On this basis, easy to expand the structure for large point FFT operations.
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Size: 128000 |
Author: culun |
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Description: Dana Quade in 1979 proposed a test that is often more powerful than the Friedman test. It also eliminates block differences but weights the raw data indicate possibly more marked treatment effects. Whereas the Friedman test is basically an extension of the sign test, the Quade test is effectively an extension of the Wilcoxon signed rank test and is equivalent to it when the treatments are two.
Platform: |
Size: 2048 |
Author: redasu |
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Description: 1.
Top module name : SHIFTER (File name : SHIFTER.v)
2.
Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3.
Output pins: OUT [15:0].
4.
Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge.
5.
The SHIFT signal describes the shift number. The shift range is 0 to 15.
6.
When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left.
7.
When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low.
8.
You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
9.
The logarithmic shifter is based on a staged approach (powers of 2). A simple architecture is described as Figure 1.
Platform: |
Size: 6144 |
Author: chen-che,wemg |
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Description: 用verilog实现一个8阶的改进串行FIR低通滤波器，输入数据位宽为12比特,经符号扩展后变为13比特。-With verilog order to achieve an improvement of 8 serial FIR low-pass filter, the input data bit width of 12 bits by sign extension into a 13-bit after.
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Size: 1024 |
Author: hgdlsl |
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Description: DS18B20是DALLAS公司生产的一线式数字温度传感器，具有3引脚TO－92小体积封装形式；温度测量范围为－55℃～＋125℃,可编程为9位～12位A/D转换精度，测温分辨率可达0.0625℃，被测温度用符号扩展的16位数字量方式串行输出，支持3V～5.5V的电压范围，使系统设计更灵活、方便；其工作电源既可在远端引入，也可采用寄生电源方式产生-DALLAS DS18B20 is produced by first-line digital temperature sensor, a 3-pin TO-92 small-size package temperature measurement range is-55 ℃ ~+125 ℃, programmed for the 9 ~ 12-bit A/D conversion precision, the measured Temperature resolution up to 0.0625 ℃, the measured temperature of 16-bit with sign extension mode digital serial output, 3V ~ 5.5V voltage range, making the system design more flexible and convenient its work in the remote power supply can introduce , may also have parasitic power mode
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Size: 56320 |
Author: kyky |
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Description: 8086 汇编语言六大编程指令集
一、数据传输指令
它们在存贮器和寄存器、寄存器和输入输出端口之间传送数据.
1. 通用数据传送指令.
MOV 传送字或字节.
MOVSX 先符号扩展,再传送.
MOVZX 先零扩展,再传送.
PUSH 把字压入堆栈.
POP 把字弹出堆栈. -8086 assembly language instruction set a six programming, data transfer instructions are in memory and registers, register and transfer data between the input and output port 1. Universal data transfer instructions. MOV send word or byte. MOVSX first sign extension, retransmission. MOVZX first zero-extended, re-transmission. PUSH the word onto the stack. POP to words pop the stack. ...
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Size: 2048 |
Author: Alice |
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Description: VHDL语言中的符号扩展方法,方法简单可靠，可以用来快速编写 vhdl程序，希望对大家有帮助。-VHDL language sign extension method, the method is simple and reliable, can be used to quickly write vhdl program, we hope to help.
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Size: 1024 |
Author: ls112853 |
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Description: A 32-bit ARC PROM pass arguments and environment as 32-bit pointer. These macros take care of sign extension.
Platform: |
Size: 1024 |
Author: tuebuikd |
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Description: 一个比较新颖的思路将运算表达式转换为二叉树，支持括号，若需要支持其他复杂符号扩展也比较容易。-A relatively new idea will be converted to binary arithmetic expression, support brackets, but also relatively easy if you need to support other complex sign extension.
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Size: 14336 |
Author: uncleheart |
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Description: nVidia Hardware Documentation (09.03.21):
Bit operations
Sign extension
Bitfield extraction
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Size: 1483857 |
Author: SergeXY1 |
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