Search - simulink verilog

Search - simulink verilog - List

[VHDL-FPGA-Verilog] FSKDFSK DL : 1: fsk调制与解调，此程序经过验证，可以运用，通讯方面的同学可以用-FSK modulation and demodulation, this procedure has been verified and can use communications students can use
Update : 2025-02-19 Size : 3kb Publisher : we
[matlab] am DL : 0: AM调制及单边带调制程序规范易懂,It will be helpful to you!-AM modulated single-sideband modulation procedures and norms understandable, It will be helpful to you!
Update : 2025-02-19 Size : 1kb Publisher : 凌珏
[VHDL-FPGA-Verilog] OFDMcode DL : 0: OFDM 的 VHDL 实现分块实现. 功能强大 -OFDM block of VHDL realize realize. Powerful
Update : 2025-02-19 Size : 38kb Publisher : 付文强
[Multimedia program] DDC_FilterChain_HDL DL : 0: simulink demo of ddc
Update : 2025-02-19 Size : 169kb Publisher : bnpvas
[VHDL-FPGA-Verilog] pll DL : 0: 模拟锁相环（apll）的一些simulink模型-Analog phase-locked loop (apll) some simulink model
Update : 2025-02-19 Size : 717kb Publisher : prescaler
[VHDL-FPGA-Verilog] DES DL : 0: DES加密算法的VHDL实现,采用流水线技术实现-The VHDL implement of DES encrypt algorithmic
Update : 2025-02-19 Size : 16.9mb Publisher : Mr Yang
[Other] Freq_Divider DL : 0: frequency divider using verilog
Update : 2025-02-19 Size : 1kb Publisher : hazwaj
[VHDL-FPGA-Verilog] HDLImplementationoftheVariableStepSize DL : 0: proposes a Verilog implementation of the Normalized Least Mean Square (NLMS) adaptive algorithm, having a variable step size. The envisaged application is the identification of an unknown system. First the convergence of derived LMS algorithms was analyzed in a Simulink application.
Update : 2025-02-19 Size : 218kb Publisher : 陳柏宇
[Other] proiect DL : 0: Fir filter implemented in verilog and tasted. also conteins the implementation in simulink
Update : 2025-02-19 Size : 1.76mb Publisher : valentina199114
[3G develop] BPSK_receiver DL : 0: BPSK接收机设计，能够通过Synplify DSP直接生成Verilog代码。-BPSK Reciver model. This simulink model can generate RTL code via Synplify DSP.
Update : 2025-02-19 Size : 20kb Publisher : bigdot
[Wavelet] dct2d DL : 0: 2D-DCT, 二维离散余弦变换模型。能够通过Synplify DSP生成Verilog代码 -2D-DCT model. This simulink model can generate RTL code via Synplify DSP.
Update : 2025-02-19 Size : 25kb Publisher : bigdot
[VHDL-FPGA-Verilog] PC-CFR DL : 5: 采用matlab simulink编写的消峰参考设计，可以直接生成verilog代码。消峰主要用于降低无线信号的峰均比，提高功放效率。-Clipping prepared using matlab simulink reference design, you can generate verilog code directly. Consumers peak mainly used to reduce radio signal PAR, improve power amplifier efficiency.
Update : 2025-02-19 Size : 2.49mb Publisher :
[Software Engineering] digital-DC_DC-control-chip DL : 0: 复旦大学数字DCDC控制芯片设计利用matlab中simulink建模 verilog语言实现对于芯片设计有较大参考价值-Fudan University digital DCDC control chip design using Simulink matlab modeling Verilog language to achieve a larger reference value for the design of the chip
Update : 2025-02-19 Size : 9.88mb Publisher : 马戎
[matlab] verilog DL : 0: this is another impact to the simulations
Update : 2025-02-19 Size : 45kb Publisher : teck
[VHDL-FPGA-Verilog] FpgaFskMod DL : 0: 基于verilog的2FSK调制程序，simulink仿真通过(2FSK modulation program based on Verilog, Simulink simulation passed)
Update : 2025-02-19 Size : 951kb Publisher : 坏小伙