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[VHDL-FPGA-Verilog] FSKDFSK

Description: fsk调制与解调，此程序经过验证，可以运用，通讯方面的同学可以用-FSK modulation and demodulation, this procedure has been verified and can use communications students can use
Platform: | Size: 3072 | Author: we | Hits:

[matlab] am

Description: AM调制及单边带调制 程序规范易懂,It will be helpful to you!-AM modulated single-sideband modulation procedures and norms understandable, It will be helpful to you!
Platform: | Size: 1024 | Author: 凌珏 | Hits:

[VHDL-FPGA-Verilog] OFDMcode

Description: OFDM 的 VHDL 实现 分块实现. 功能强大 -OFDM block of VHDL realize realize. Powerful
Platform: | Size: 38912 | Author: 付文强 | Hits:

[Multimedia program] DDC_FilterChain_HDL

Description: simulink demo of ddc
Platform: | Size: 173056 | Author: bnpvas | Hits:

[VHDL-FPGA-Verilog] pll

Description: 模拟锁相环（apll）的一些simulink模型-Analog phase-locked loop (apll) some simulink model
Platform: | Size: 734208 | Author: prescaler | Hits:

[VHDL-FPGA-Verilog] DES

Description: DES加密算法的VHDL实现,采用流水线技术实现-The VHDL implement of DES encrypt algorithmic
Platform: | Size: 17718272 | Author: Mr Yang | Hits:

[Other] Freq_Divider

Description: frequency divider using verilog
Platform: | Size: 1024 | Author: hazwaj | Hits:

[VHDL-FPGA-Verilog] HDLImplementationoftheVariableStepSize

Description: proposes a Verilog implementation of the Normalized Least Mean Square (NLMS) adaptive algorithm, having a variable step size. The envisaged application is the identification of an unknown system. First the convergence of derived LMS algorithms was analyzed in a Simulink application.
Platform: | Size: 223232 | Author: 陳柏宇 | Hits:

[Other] proiect

Description: Fir filter implemented in verilog and tasted. also conteins the implementation in simulink
Platform: | Size: 1844224 | Author: valentina199114 | Hits:

[3G develop] BPSK_receiver

Description: BPSK接收机设计，能够通过Synplify DSP直接生成Verilog代码。-BPSK Reciver model. This simulink model can generate RTL code via Synplify DSP.
Platform: | Size: 20480 | Author: bigdot | Hits:

[Wavelet] dct2d

Description: 2D-DCT, 二维离散余弦变换模型。能够通过Synplify DSP生成Verilog代码 -2D-DCT model. This simulink model can generate RTL code via Synplify DSP.
Platform: | Size: 25600 | Author: bigdot | Hits:

[VHDL-FPGA-Verilog] PC-CFR

Description: 采用matlab simulink编写的消峰参考设计，可以直接生成verilog代码。消峰主要用于降低无线信号的峰均比，提高功放效率。-Clipping prepared using matlab simulink reference design, you can generate verilog code directly. Consumers peak mainly used to reduce radio signal PAR, improve power amplifier efficiency.
Platform: | Size: 2606080 | Author: | Hits:

[Software Engineering] digital-DC_DC-control-chip

Description: 复旦大学 数字DCDC控制芯片设计 利用matlab中simulink建模 verilog语言实现 对于芯片设计有较大参考价值-Fudan University digital DCDC control chip design using Simulink matlab modeling Verilog language to achieve a larger reference value for the design of the chip
Platform: | Size: 10362880 | Author: 马戎 | Hits:

[matlab] verilog

Description: this is another impact to the simulations
Platform: | Size: 46080 | Author: teck | Hits:

[VHDL-FPGA-Verilog] FpgaFskMod

Description: 基于verilog的2FSK调制程序，simulink仿真通过(2FSK modulation program based on Verilog, Simulink simulation passed)
Platform: | Size: 973824 | Author: 坏小伙 | Hits:

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