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[Other resource] sin

Description: 正弦信号发生器程序,用VERILOG写出。
Platform: | Size: 2529457 | Author: 112254 | Hits:

[VHDL-FPGA-Verilog] 8bitsine

Description: 8bit采样sine波形发生器,一共两个文件，各自用VHDL和VERILOG编写，通信开发平台专用-8bit sampling sine wave generator, a total of two papers, each with VHDL and VERILOG preparation, communications development platform dedicated
Platform: | Size: 5120 | Author: 王刚 | Hits:

[Other] VerilogandVHDL

Description: Verilog and VHDL状态机设计，英文pdf格式 State machine design techniques for Verilog and VHDL Abstract : Designing a synchronous finite state Another way of organizing a state machine (FSM) is a common task for a digital logic only one logic block as shown in engineer. This paper will discuss a variety of issues regarding FSM design using Synopsys Design Compiler . Verilog and VHDL coding styles will be 2.0 Basic HDL coding presented. Different methodologies will be compared using real-world examples.-Verilog and VHDL state machine design, English pdf format State machine design techniques for Ve rilog and VHDL Abstract : Designing a synchronous finite state Another w ay of organizing a state machine (FSM) is a commo n task for a digital logic only one logic block as shown in engineer. This paper will discuss a var iety of issues regarding FSM design using Synop sys Design Compiler. Verilog and VHDL coding st yles will be 2.0 Basic HDL coding presented. Dif ferent methodologies will be compared using're al-world examples.
Platform: | Size: 113664 | Author: mingming | Hits:

[VHDL-FPGA-Verilog] Sintab_Altera

Description:
Platform: | Size: 503808 | Author: helei_zju | Hits:

[assembly language] sine

Description: 用verilog语言编的正弦波发生器，可以用QuartusII来打开这个源码，也可以转换成VHDL语言-Verilog language prepared by the sine wave generator can be used QuartusII to open the source code can also be converted into VHDL language
Platform: | Size: 104448 | Author: 雨孩 | Hits:

[Other Embeded program] verilog_sin_complete

Description: verilog设计正弦波波形模块,可自己通过参数设置得到所需峰值的波形-Verilog design module sinusoidal waveform can be themselves through the necessary parameters of the waveform peak
Platform: | Size: 3072 | Author: 刘彬 | Hits:

[VHDL-FPGA-Verilog] sinfunction

Description: 用cordic算法实现超越函数,sin,cos用此方法也可以实现其他的sinhx,coshx,ex.代码用verilog编写-CORDIC algorithm with transcendental function, sin, cos by this method can also realize other sinhx, coshx, ex. Verilog code used to prepare
Platform: | Size: 236544 | Author: yu_leo | Hits:

[VHDL-FPGA-Verilog] sin

Description: 正弦信号发生器程序,用VERILOG写出。-Sinusoidal signal generator procedures, used to write Verilog.
Platform: | Size: 2529280 | Author: 112254 | Hits:

[VHDL-FPGA-Verilog] sin.tar

Description: 神奇的sin波生成verilog源码，非常简单的代码无需乘法即可生成sin,cos，值得搞算法的人借鉴-Magic sin wave generated Verilog source code, the code is very simple multiplication can be generated without sin, cos, worthy people from engaging in algorithm
Platform: | Size: 2048 | Author: yangyu | Hits:

[VHDL-FPGA-Verilog] custom_cordic

Description: verilog编程开发的cordic例程，计算SIN,COS功能与计算幅值角度功能可设定，运算宽度可设定，并有完善的TESTBENCH。-Verilog programming developed CORDIC routines to calculate SIN, COS function and calculating the amplitude of the perspective of function can be set, computing the width can be set, and perfect TESTBENCH.
Platform: | Size: 119808 | Author: yangyu | Hits:

[VHDL-FPGA-Verilog] sin

Description: 用Verilog语言在FPGA内实现一256个采样点的正弦波，已尝试，挺好用的-Verilog language used in the FPGA to achieve one of the 256 sampling points sine wave, I have already tried it, very useful~ ~ ~
Platform: | Size: 104448 | Author: | Hits:

[VHDL-FPGA-Verilog] CordicNCO

Description: 基于CORDIC算法的，数字控制振荡器的设计。带测试程序，输入一个振荡频率，输出SIN和COS的波形！-Based on the CORDIC algorithm, the digital controlled oscillator design. With test procedures, enter a oscillation frequency, the output waveform SIN and COS!
Platform: | Size: 4096 | Author: 咚咚 | Hits:

[VHDL-FPGA-Verilog] RomNCO

Description: 基于NCO的数字控制振荡器。带测试程序，输出12位的COS和SIN波形。-Based on the digital control oscillator NCO. With test procedures, the output 12 of the COS and the SIN waveform.
Platform: | Size: 29696 | Author: 咚咚 | Hits:

[VHDL-FPGA-Verilog] sin

Description: QUARTUSS||环境下的简易正弦信号发生器的设计，VERILOG 代码，用到了嵌入式逻辑分析仪-QUARTUSS | | environment simple sinusoidal signal generator, VERILOG code, use the embedded logic analyzer
Platform: | Size: 2955264 | Author: sujiebin | Hits:

[Other] coredic-verilog

Description: 采用Verilog硬件描述语言实现的三角函数sin(),cos()转换的部分代码-Adopt Verilog hardware description language realization trigonometric sin (), cos () conversion part code
Platform: | Size: 38912 | Author: sharbel | Hits:

[VHDL-FPGA-Verilog] sin

Description: 基于verilog的正选函数 简单实用 初学者的好材料-Verilog function based on the simple and practical choice for beginners is a good material
Platform: | Size: 81920 | Author: majianbiao | Hits:

[VHDL-FPGA-Verilog] cordic

Description: 在QUARTUS环境下，通过Verilog实现cordic，产生sin，cos-In QUARTUS environment, through the Verilog implementation cordic, generate sin, cos
Platform: | Size: 1709056 | Author: 洪依 | Hits:

[VHDL-FPGA-Verilog] sin_producer

Description: VERILOG语言，查找表方法 实现了 典型的 正弦波 发生器-verilog sin signal producer
Platform: | Size: 4978688 | Author: liujia | Hits:

[VHDL-FPGA-Verilog] 123_ise9migration

Description: DDS正弦信号发生器verilog的功能强大很实用-dds sin verilog
Platform: | Size: 288768 | Author: 亮晶晶 | Hits:

[VHDL-FPGA-Verilog] DDS-SIN

Description: 用verilog语言实现DDS的正弦波发送-DDS sine wave sent verilog language
Platform: | Size: 2629632 | Author: 牛倩 | Hits:
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