Search - sin wave using vhdl

[VHDL-FPGA-Verilog] sin

Description: 基于Quartus II 5.0编写的正弦波发生器，可控频率，用vhdl编写的-Quartus II 5.0 on the preparation of the sine wave generator, controllable frequency, prepared using VHDL
Platform: | Size: 475136 | Author: uuk | Hits:

[VHDL-FPGA-Verilog] sin

Description: 基于fpga的正弦波发生器设计，有一定的参考价值，写的比较详细-The sine wave generator based on FPGA design, have a certain reference value, a more detailed written
Platform: | Size: 632832 | Author: qlg | Hits:

[Wavelet] singt

Description: 实现了方波、正弦波、三角波的输出，同时在LCD模块中用状态机的方法实现LCD的对应显示：当输出正弦波，LCD显示“SIN”；当输出方波，LCD显示“REC”；当输出三角波，显示“TRI”；复位和其它位置波形显示“UNI”。-Realize a square wave, sine wave, triangle wave output, while in the LCD module using the state machine approach to achieve the corresponding LCD display: When the output sine wave, LCD display
Platform: | Size: 1062912 | Author: Emma | Hits:

[VHDL-FPGA-Verilog] VHDL(sin)

Description: 基于ROM的正弦波发生器的设计一．实验目的 1. 学习VHDL的综合设计应用 2. 学习基于ROM的正弦波发生器的设计二．实验内容设计基于ROM的正弦波发生器，对其编译，仿真。具体要求： 1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成 2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。 3.将50MHz作为输入时钟。 -ROM-based sine wave generator design 1. Purpose of the experiment 1. VHDL Integrated Design and Application of Learning 2. Learning ROM-based sine wave generator design 2. Experimental content ROM-based sine wave generator design, its compilation, simulation. Specific requirements: 1. Sine wave generator by the data storage module (ROM), waveform generator control module and latch modules Two. Waveform data storage module (ROM) custom data width is 8, the address width of 6, can store 64-point sine wave data, wave data obtained using MATLAB. 3. The 50MHz input clock.
Platform: | Size: 17408 | Author: 爱好 | Hits:

[VHDL-FPGA-Verilog] sin

Description: 基于VHDL硬件描述语言的正弦波利用Maxplus的仿真实例-VHDL hardware description language based on the sine wave using the simulation Maxplus
Platform: | Size: 411648 | Author: dongmei | Hits:

[Wavelet] the-realization-of-sin

Description: 利用VHDL语言，实现正弦波的产生，在此程序中，利用计数器原理实现-Using VHDL language, sine wave generation, in this procedure, the use of counter principle to achieve
Platform: | Size: 4096 | Author: 布拉格宝贝 | Hits:

[VHDL-FPGA-Verilog] sin

Description: 用VHDL语言编写实现以下功能：用PLL，复位器，分频器，同步时钟，计数器来产生正弦波，再在其上加扰，用FIR滤波器进行滤波整形，最后得到输出。-Using VHDL language to achieve the following functions: PLL, reset, clock synchronization, frequency divider, counter to generate sine wave, and then scrambling on the filter shaping filter with FIR, finally get the output.
Platform: | Size: 6779904 | Author: 猪头 | Hits:

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[VHDL-FPGA-Verilog] sin

[VHDL-FPGA-Verilog] sin

[Wavelet] singt

[VHDL-FPGA-Verilog] VHDL(sin)

[VHDL-FPGA-Verilog] sin

[Wavelet] the-realization-of-sin

[VHDL-FPGA-Verilog] sin

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