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[Other resource] sin-lookup-table

Description: 基于嵌入式的正弦查表程序.在sintable.asm中定义的正弦表.系统频率设置49.152MHz，强振模式.-based embedded sine chat program. Sintable.asm defined in the sine table. System set the frequency 49.152 MHz, strong vibration mode.
Platform: | Size: 9360 | Author: kevin | Hits:

[Other resource] DDS_Power

Description: FPGA上的VERILOG语言编程。通过查找表实现直接数字频率合成。在主控部分通过键盘选择正弦波，方波，三角波，斜波，以及四种波形的任意两种的叠加，以及四种波形的叠加；通过控制频率控制字C的大小，以控制输出波形频率，实现1Hz的微调；通过地址变换实现波形相位256级可调；通过DAC0832使波形幅值256级可调；通过FPGA内部RAM实现波形存储回放；并实现了每秒100HZ扫频。-FPGA on the verilog language programming. Lookup table through direct digital frequency synthesis. In part through the control of the keyboard to choose sine, square, triangle wave, sloping wave, and four arbitrary waveform two superposed and the stack of four waveform; by controlling the frequency control word on the size, in order to control the output waveform frequency, 1 Hz to achieve the fine-tuning; Address transform through waveform phase adjustable 256; DAC0832 so through waveform amplitude adjustable 256; FPGA through internal RAM to the waveform storage intervals; and achieve a 100 per second sweep 9999.
Platform: | Size: 16232 | Author: 田世坤 | Hits:

[SCM] sin-lookup-table

Description: 基于嵌入式的正弦查表程序.在sintable.asm中定义的正弦表.系统频率设置49.152MHz，强振模式.-based embedded sine chat program. Sintable.asm defined in the sine table. System set the frequency 49.152 MHz, strong vibration mode.
Platform: | Size: 9216 | Author: kevin | Hits:

[VHDL-FPGA-Verilog] DDS_Power

Description: FPGA上的VERILOG语言编程。通过查找表实现直接数字频率合成。在主控部分通过键盘选择正弦波，方波，三角波，斜波，以及四种波形的任意两种的叠加，以及四种波形的叠加；通过控制频率控制字C的大小，以控制输出波形频率，实现1Hz的微调；通过地址变换实现波形相位256级可调；通过DAC0832使波形幅值256级可调；通过FPGA内部RAM实现波形存储回放；并实现了每秒100HZ扫频。-FPGA on the verilog language programming. Lookup table through direct digital frequency synthesis. In part through the control of the keyboard to choose sine, square, triangle wave, sloping wave, and four arbitrary waveform two superposed and the stack of four waveform; by controlling the frequency control word on the size, in order to control the output waveform frequency, 1 Hz to achieve the fine-tuning; Address transform through waveform phase adjustable 256; DAC0832 so through waveform amplitude adjustable 256; FPGA through internal RAM to the waveform storage intervals; and achieve a 100 per second sweep 9999.
Platform: | Size: 16384 | Author: 田世坤 | Hits:

[assembly language] sine

Description: 用verilog语言编的正弦波发生器，可以用QuartusII来打开这个源码，也可以转换成VHDL语言-Verilog language prepared by the sine wave generator can be used QuartusII to open the source code can also be converted into VHDL language
Platform: | Size: 104448 | Author: 雨孩 | Hits:

[matlab] address_sin

Description: 正弦值查找表是用matlab代码写的，根据量化地址来查找实际地址的正弦值-Sine value lookup table is written in matlab code, according to quantify the address to find the actual address of the sine value
Platform: | Size: 1024 | Author: 文书 | Hits:

[assembly language] dsp-sin

Description: 汇编语言产生的查表法实现正弦波发生器的程序，需要的下载。-Assembly language generated by sine wave generator look-up table method implementation procedures, the required download.
Platform: | Size: 2048 | Author: 杨树涛 | Hits:

[Energy industry] sin_cos_lookup_generator

Description: Generator of sine and cosine lookup tables in Matlab.
Platform: | Size: 3072 | Author: Evgenije | Hits:

[DSP program] SineWaveGeneration

Description: This zip folder contains the sine wave generation using lookup table. Implemenated on BF533 VDSP-This zip folder contains the sine wave generation using lookup table. Implemenated on BF533 VDSP++
Platform: | Size: 47104 | Author: Jaganathan | Hits:

[VHDL-FPGA-Verilog] vhdl2

Description: vhdl语言正弦信号发生器设计，传统的用分立元件或通用数字电路元件设计电子线路的方法设计周期长,花费大, 可移植性差。本文以正弦波发生器为例,利用EDA 技术设计电路,侧重叙述了用VHDL 来完 成直接数字合成器(DDS) 的设计,DDS 由相位累加器和正弦ROM 查找表两个功能块组成,其 中ROM查找表由兆功能模块LPM-ROM来实现。-The traditional use of discrete components or general purpose digital circuit design method of electronic circuit design cycle is long, expensive, poor portability. In this paper, sine wave generator, for example, circuit design using EDA technology, focusing on the use of VHDL description to complete the direct digital synthesizer (DDS) design, DDS ROM from the phase accumulator and sine lookup table composed of two functional blocks, including ROM lookup table by the LPM-ROM modules trillion to implement.
Platform: | Size: 94208 | Author: 枫蓝 | Hits:

[VHDL-FPGA-Verilog] ROM

Description: Verilog sine的查找表，相信大家会用到-Verilog sine lookup table, I believe we will use
Platform: | Size: 3072 | Author: wuzhongpeng | Hits:

[VHDL-FPGA-Verilog] SG_FPGA

Description: 2006年电子设计竞赛二等奖，多功能函数、信号发生器核心器件FPGA内部的原理图，主要模块用VHDL代码描述，包括PLL、相位累加器、波形算法和正弦波查找表，可实现0.005Hz~20MHz的多波形信号产生，频率步进值0.005，输出接100MSPS速率的DAC--AD9762-Electronic Design Competition 2006, second prize, multi-function signal generator within the core of the device schematic FPGA, VHDL code with the description of the main modules, including the PLL, phase accumulator, sine lookup table algorithm and the waveform can be realized 0.005Hz ~ 20MHz multi-waveform signal generator, the frequency step value of 0.005, then the output rate of 100MSPS DAC- AD9762
Platform: | Size: 1099776 | Author: zlz | Hits:

[VHDL-FPGA-Verilog] Rendering_primitives

Description: Some 2D graphic rendering in VHDL: - Line - Draw a line - Circle - Draw circle - BitBLT - Draw a rectangle - Sine and cosinus lookup tables - Rotation - Rotate line
Platform: | Size: 13312 | Author: lance_corona | Hits:

[VHDL-FPGA-Verilog] DDS4.mdl

Description: DDS(快速正交调制）生成正弦波形，利用相位累加字进行累加，查找查找表内容输出正弦数据，在通信领域应用很多，我采用的是matlab的simulink进行前期仿真-DDS (fast quadrature modulation) to generate sine wave, the use of the word to accumulate phase accumulation, content output sine lookup table lookup data in many applications in the communications field, I used to pre simulink of matlab simulation
Platform: | Size: 12288 | Author: lu | Hits:

[VHDL-FPGA-Verilog] DDS

Description: DDS信号生成模块，使用MATLAB产生查找表，可输出方波、三角波、锯齿波、正弦波-DDS signal generator module, using MATLAB to generate a lookup table can output square wave, triangle wave, sawtooth, sine
Platform: | Size: 8883200 | Author: 苏杭 | Hits:

[Other] DDS

Description: 本设计基于数字频率合成技术,采用正弦查找表实现波形产生.直接数字频率合成技术（DDS）是一种先进的电路结构，能在全数字下对输出信号频率进行精确而快速的控制，DDS技术还在解决输出信号频率增量选择方面具有很好的应用，DDS所产生的信号具有频率分辨率高、频率切换速度快、频率切换时相位连续、输出相位噪声低和可以产生任意波形等诸多优点。 文中介绍了DDS的基本原理，对DDS的质谱及其散杂抑制进行了分析。程序设计采用超高速硬件描述语言VHDL描述DDS,在此基础上设计了正弦波、三角波、方波等信号发生器，。完成了软件和硬件的设计，以及实验样机的部分调试。-The design is based digital frequency synthesizer technology, using a sine lookup table to achieve waveform generation. Direct digital frequency synthesis (DDS) is an advanced circuit structure can fully digital output signal frequency under precise and fast control, DDS technology also solve the incremental output signal frequency selection signal having a very good application, DDS generated by high frequency resolution, frequency switching speed, phase-continuous frequency switching time, low phase noise output and can generate arbitrary waveforms, and many other advantages . This paper introduces the basic principles of the DDS, DDS MS for its bulk inhibition were analyzed. Programming using ultra high-speed hardware description language VHDL description DDS, on the basis of the design of the sine wave, triangle wave, square wave signal generator. Completed part of debugging software and hardware design, and the experimental prototype.
Platform: | Size: 4485120 | Author: 冯阳 | Hits:

[SCM] lab11

Description: 在dac 上显示一个波图，刚刚输出的时候是sine 的图 开动按钮后发出不同的图像-Write a C program that creates a waveform generator. It should start by outputting a sine wave to DAC0. Each time SW1 is pressed then released, the wave form should change, first to a triangle wave, then a sawtooth wave, then back to a sine wave (repeating forever). Each time SW2 is pressed and released, the output amplitude should be adjusted by a factor of 2 (full amplitude, then half amplitude, then quarter amplitude, then back to full amplitude, etc.). Use the 2.5V internal reference the ADC12 module. The full amplitude for each wave form should be 0V to 2.5V, one period should contain 256 samples, and the frequency should be 15 Hz. You should use MATLAB to create waveform lookup tables for the sine and triangle waveforms. For the sawtooth wave, you can either use MATLAB or an internal function to generate the waveform.
Platform: | Size: 2048 | Author: kailing | Hits:

[VHDL-FPGA-Verilog] sin_en

Description: DDS 由相位增量器，相位累加器，量化器以及正余弦查找表四部分组成。 相位累加器每一周期会累加上固定的相位值，然后从查找表中找到对应的数值。-DDS by the phase increment, phase accumulator, quantizer and sine and cosine lookup table of four parts. The phase accumulator accumulates a fixed phase value for each period, and then finds the corresponding value the lookup table. .
Platform: | Size: 2712576 | Author: panda | Hits:

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