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[VHDL-FPGA-Verilog] 8bitsine

Description: 8bit采样sine波形发生器,一共两个文件，各自用VHDL和VERILOG编写，通信开发平台专用-8bit sampling sine wave generator, a total of two papers, each with VHDL and VERILOG preparation, communications development platform dedicated
Platform: | Size: 5120 | Author: 王刚 | Hits:

[VHDL-FPGA-Verilog] DDS_Power

Description: FPGA上的VERILOG语言编程。通过查找表实现直接数字频率合成。在主控部分通过键盘选择正弦波，方波，三角波，斜波，以及四种波形的任意两种的叠加，以及四种波形的叠加；通过控制频率控制字C的大小，以控制输出波形频率，实现1Hz的微调；通过地址变换实现波形相位256级可调；通过DAC0832使波形幅值256级可调；通过FPGA内部RAM实现波形存储回放；并实现了每秒100HZ扫频。-FPGA on the verilog language programming. Lookup table through direct digital frequency synthesis. In part through the control of the keyboard to choose sine, square, triangle wave, sloping wave, and four arbitrary waveform two superposed and the stack of four waveform; by controlling the frequency control word on the size, in order to control the output waveform frequency, 1 Hz to achieve the fine-tuning; Address transform through waveform phase adjustable 256; DAC0832 so through waveform amplitude adjustable 256; FPGA through internal RAM to the waveform storage intervals; and achieve a 100 per second sweep 9999.
Platform: | Size: 16384 | Author: 田世坤 | Hits:

[VHDL-FPGA-Verilog] sinewave

Description: 6通道正弦波发生器，产生频率，相位，幅值都可调的正弦波形-6-channel sine wave generator, resulting in frequency, phase, amplitude of the sinusoidal waveform are adjustable
Platform: | Size: 1024 | Author: 桑武斌 | Hits:

[VHDL-FPGA-Verilog] sin

Description: 用Verilog语言在FPGA内实现一256个采样点的正弦波，已尝试，挺好用的-Verilog language used in the FPGA to achieve one of the 256 sampling points sine wave, I have already tried it, very useful~ ~ ~
Platform: | Size: 104448 | Author: | Hits:

[SCM] signal

Description: verilog写的串口控制信号发生器，能通过用串口控制产生正弦波方波等信号-written in verilog serial control signal generator, can be generated using serial control, such as sine wave square wave signals
Platform: | Size: 5519360 | Author: ray | Hits:

[VHDL-FPGA-Verilog] DDS-top

Description: 能够基于DDS实现输出正弦波形的一部分程序，利用Verilog HDL语言编写。-Able to achieve based on the DDS output sine wave-shaped part of the procedure, the use of Verilog HDL language.
Platform: | Size: 299008 | Author: evil | Hits:

[VHDL-FPGA-Verilog] dds_easy

Description: 直接频率合成DDS模块的ise工程，可以直接下载，在Spartan3/Spartan3E上验证通过。该DDS模块可以产生双通道的不同频率的正弦波，也可以产生同频的任意相位差的相移波形。本模块累加器位数为32位，可以产生12位相位精度12位量化精度的正弦波。该设计例化一个Block Ram，为节省储存空间仅需要储存1/4周期的数据。根据需要，可以重新修改数据，改变波形。-DDS direct frequency synthesizer module ，ise project, can be directly downloaded through the Spartan3/Spartan3E and tested successfully. The DDS module can generate two-channel sine wave of different frequency, or produce the same frequency arbitrary waveform phase difference of the phase shift. There is a 32-bit accumulator to generate 12 bit phase-precision 12-bit quantization precision of the sine wave. Cases the design of a Block Ram, in order to save storage space need to store only 1/4 cycle of data. Necessary, can modify data, change the waveform.
Platform: | Size: 471040 | Author: 郭先生 | Hits:

[SCM] dds_var

Description: 自己写的一个简单的DDS控制器，此程序包包含完整的VERILOG写的程序，操作有点简单，输出正弦波，方波，锯齿波，通过键盘可以选择输出波形，与大家共享-To write a simple DDS controller, this package contains a complete program written in VERILOG, a bit simple to operate, the output sine wave, square wave, sawtooth, through the keyboard can select output waveform, and for all to share
Platform: | Size: 1184768 | Author: deng | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 我们小组共了一个月做的DDS,程序核心用的是Verilog HDL,有仿真波形,输出正弦波,方波,及三角波,步进可调.频率范围1HZ--10MHZ-Our group for a month to do a total of DDS, the procedure is used in the core of Verilog HDL, there are simulation waveform, the output sine wave, square wave and triangular wave, step adjustable. Frequency range 1HZ- 10MHZ
Platform: | Size: 117760 | Author: tiancheng | Hits:

[VHDL-FPGA-Verilog] DDS_FINAL

Description: My project is on Direct Digital Synthesiser using Verilog HDL.This project is doing by me on july 2009 in summer training at NIT Kurukshetra, India. This DDS system generate the square wave, Triangular wave,Sine wave and saw wave with different frequency. We can change the frequency using frequency selector input. Please accept this project. We use the SPARTAN 3E 500 device to implement it.
Platform: | Size: 437248 | Author: Raju Kumar | Hits:

[VHDL-FPGA-Verilog] fullsine

Description: This a code for sine wave generation in modelsim. The code is written in verilog. An LUT has to be added to this program to work completely.-This is a code for sine wave generation in modelsim. The code is written in verilog. An LUT has to be added to this program to work completely.
Platform: | Size: 1024 | Author: Jithu | Hits:

[Compress-Decompress algrithms] asias_dds

Description: 一个简易的信号源，具有多种波形发生功能还有扫频，调制，频率计等相关功能-My project is on Direct Digital Synthesiser using Verilog HDL.This project is doing by me on july 2009 in summer training at NIT Kurukshetra, India. This DDS system generate the square wave, Triangular wave,Sine wave and saw wave with different frequency
Platform: | Size: 31744 | Author: david | Hits:

[Embeded Linux] 83390078DDS

Description: DDS的工作原理是以数控振荡器的方式产生频率、相位可控制的正弦波。电路一般包括基准时钟、频率累加器、相位累加器、幅度/相位转换电路、D/A转换器和低通滤波器（LPF）。频率累加器对输入信号进行累加运算，产生频率控制数据X（frequency data或相位步进量）。相位累加器由N位全加器和N位累加寄存器级联而成，对代表频率的2进制码进行累加运算，是典型的反馈电路，产生累加结果Y。幅度/相位转换电路实质上是一个波形寄存器，以供查表使用。读出的数据送入D/A转换器和低通滤波器。-DDS works the way we are digitally controlled oscillator frequency, phase controlled sine wave. Circuits generally include reference clock, frequency accumulator, phase accumulator, amplitude/phase converter circuit, D/A converter and low-pass filter (LPF). The frequency accumulator to accumulate the input signal operation to produce the frequency control data X (frequency data or phase stepping volume). From the N-bit phase accumulator and the N-bit full adder cascade accumulation register is made on behalf of the frequency of the two binary codes accumulation operation, is a typical feedback circuit, resulting in cumulative results of Y. Amplitude/phase converter circuit is essentially a waveform register for look-up table to use. Read out the data into the D/A converter and low pass filter.
Platform: | Size: 44032 | Author: 394177191 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 在quartus下的DDS设计，Verilog语言，可以产生正弦波、三角波、方波等，频率可调。-Under the DDS in quartus design, Verilog language, you can produce sine wave, triangle wave, square wave, frequency adjustable.
Platform: | Size: 2632704 | Author: 米多 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 本设计中应用硬件描述语言Verilog HDL描述相位累加器，相位调制器，正弦波、方波、三角波、心电波形四个独立的波形存储器，并描述频率控制、相位控字、幅度控制单元及波形切换等相关的功能单元。-Application of the design described in Verilog HDL hardware description language phase accumulator, phase modulator, sine, square, triangle wave, the four independent ECG waveform memory, and describe the frequency control, phase control word, control unit and the waveform amplitude switching and other related functional units.
Platform: | Size: 4096 | Author: kelly | Hits:

[SCM] DDS

Description: DDS文件夹内的程序，完成直接数字频率合成功能,有正弦,三角,方波三种波形,并能扫频. 可通过键盘操作设置频率参数和选择波形种类和控制运行. 由两部分组成,"C"文件夹内,是用于在 51 单片机上运行的 C语言程序, "Verilog"文件夹内,是用Verilog语言编写的 FPGA 程序.-DDS program folder, complete direct digital frequency synthesis function, sine, triangle, square wave three, and can sweep. Can be set by keyboard operation frequency parameters and select the waveform type and control operation. Consists of two parts, " C" folder, is used to running on the microcontroller in the 51 C language program, " Verilog" folder, is written in Verilog FPGA program.
Platform: | Size: 433152 | Author: 王金 | Hits:

[VHDL-FPGA-Verilog] NEW-AD9954

Description: 一个开环的AD9954 的正弦波发生 verilog 程序。-An open loop of the AD9954 in the sine wave occurs verilog program.
Platform: | Size: 353280 | Author: 王龙 | Hits:

[VHDL-FPGA-Verilog] sinw

Description: 用verilog写的正弦波发生器，QuartusⅡ环境-Sine wave generator written in Verilog
Platform: | Size: 521216 | Author: 杀虫剂 | Hits:

[VHDL-FPGA-Verilog] verilog_dds

Description: verilog实现dds，用于FPGA产生正弦波，适用于Cyclone 2系列-verilog achieve dds, FPGA is used to generate the sine wave, in the Cyclone Series
Platform: | Size: 16789504 | Author: sunlin | Hits:

[Documents] 三角函数的Verilog HDL语言实现

Description: 以Actel FPGA作为控制核心，通过自然采样法比较1个三角载波和3个相位差为1 200的正弦波，利用Verilog HDL语言实现死区时间可调的SPWM全数字算法，并在Fushion StartKit开发板上实现SPWM全数字算法。(With Actel FPGA as the control core, between 1 and 3 triangular carrier phase difference of 1200 sine wave by natural sampling, realize the adjustable dead time using Verilog HDL language of the SPWM digital algorithm and digital SPWM algorithm is realized in Fushion StartKit development board.)
Platform: | Size: 148480 | Author: 所罗门 | Hits:
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