Description: DDS works the way we are digitally controlled oscillator frequency, phase controlled sine wave. Circuits generally include reference clock, frequency accumulator, phase accumulator, amplitude/phase converter circuit, D/A converter and low-pass filter (LPF). The frequency accumulator to accumulate the input signal operation to produce the frequency control data X (frequency data or phase stepping volume). From the N-bit phase accumulator and the N-bit full adder cascade accumulation register is made on behalf of the frequency of the two binary codes accumulation operation, is a typical feedback circuit, resulting in cumulative results of Y. Amplitude/phase converter circuit is essentially a waveform register for look-up table to use. Read out the data into the D/A converter and low pass filter.
- [shiftregister] - a shift register written in VHDL, which
- [VHDLprogrammingexamples.Rar] - some others used the VHDL source code, a
- [wave] - 89s51 do single-chip waveform generator,
- [dds] - FPGA realization of DDS, f = 90kHZ ~ 5MH
- [dds] - fpga using dds principle, have a sine wa
- [dds_v3_test3] - DDS controller in the FPGA on the realiz
- [DDS] - use Direct Digital Synthesizer realize S
- [Desktop] - DDS DDS from the phase accumulator, sine
- [m48dbl_fix] - failed to translatefailed to translatefa
- [123] - ARM ad Code
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new\AT89X55.H
...\led.c
...\9833.c
...\led.h
...\9833.LST
...\new.plg
...\9833.OBJ
...\new.hex
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...\new_Uv2.Bak
...\led.LST
...\led.OBJ
...\new.Uv2
...\new.lnp
...\new.M51
...\new_Opt.Bak
...\new.Opt
...\portconf.c
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