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[Embeded-SCM Develop] AIC

Description: 使用FPGA/CPLD设置语音AD、DA转换芯片AIC23，FPGA/CPLD系统时钟为24.576MHz 1、AIC系统时钟为12.288MHz，SPI时钟为6.144MHz 2、AIC处于主控模式 3、input bit length 16bit output bit length 16bit MSB first 4、帧同步在96KHz-The use of FPGA/CPLD set voice AD, DA conversion chip AIC23, FPGA/CPLD system clock for the 24.576MHz 1, AIC system clock is 12.288MHz, SPI clock is 6.144MHz 2, AIC is in master mode 3, input bit length 16bit output bit length 16bit MSB first 4, frame synchronization at 96KHz
Platform: | Size: 2048 | Author: 张键 | Hits:

[VHDL-FPGA-Verilog] slave_spi_ctrl

Description: SPI 的FPGA控制源代码，用于一般通用的SPI技术，FPGA/CPLD控制的AD数据采集-SPI control course code
Platform: | Size: 1024 | Author: luxiaogang | Hits:

[VHDL-FPGA-Verilog] AD9512_VHDL

Description: FPGA通过SPI总线控制Analog公司的射频时钟分配芯片的程序，在需要用到高速时钟（GHz）的电路中经常采用，比如数据采集卡及信号回放卡中会经常用到该功能，已经在产品中得到验证，工作稳定。-The VHDL code of controlling AD9512 of Analog Device
Platform: | Size: 3072 | Author: 傅其祥 | Hits:

[Linux driver] spi_adda

Description: 实现FPGA读取AD转换的数据，AD芯片我采用的是ADS7844，采用的是SPI通信方式-achieve the function of read the data from the AD transform chip.the communciation method is SPI.i have tested the code ,and it can work.
Platform: | Size: 2382848 | Author: 王晓丰 | Hits:

[VHDL-FPGA-Verilog] AD9648_ver

Description: FPGA通过SPI总线配置AD采集芯片AD9648的程序，Verilog实现 -FPGA configuration via SPI bus chip AD9648 AD acquisition procedures, Verilog realization
Platform: | Size: 1941504 | Author: 路永轲 | Hits:

[VHDL-FPGA-Verilog] MAX121_test

Description: max121，ad采集芯片，spi接口，fpga测试逻辑，verilog语言-max121, ad capture chip, spi interfaces, fpga test logic, verilog language
Platform: | Size: 6812672 | Author: 蒋大鹏 | Hits:

[VHDL-FPGA-Verilog] spi_ad

Description: FPGA与DAC芯片的SPI接口驱动，实现串行数据的传输。(Realizing the communication between FPGA and DA chip)
Platform: | Size: 6839296 | Author: xyz123 | Hits:

[Other] adc_interface-master

Description: ADC_Interface Simple SPI interface for AD7908/AD7918/AD7928 written in verilog HDL
Platform: | Size: 27648 | Author: 醉小楼 | Hits:

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