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[Other resource] IP_SPI

Description: spi总线的vhdl代码，试了试可以用。希望能对开发者有所帮助。-spi bus vhdl code Shileshi can use. The hope is to help developers.
Platform: | Size: 343909 | Author: 李鸣 | Hits:

[Other resource] SPI

Description: SPI BUS VHDL实现-VHDL SPI BUS
Platform: | Size: 853498 | Author: davidluo | Hits:

[Other resource] spi

Description: VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the \"master\" and the \"slave\". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.
Platform: | Size: 65393 | Author: 阿飞 | Hits:

[VHDL-FPGA-Verilog] IP_SPI

Description: spi总线的vhdl代码，试了试可以用。希望能对开发者有所帮助。-spi bus vhdl code Shileshi can use. The hope is to help developers.
Platform: | Size: 344064 | Author: 李鸣 | Hits:

[VHDL-FPGA-Verilog] SPI

Description: SPI BUS VHDL实现-VHDL SPI BUS
Platform: | Size: 852992 | Author: davidluo | Hits:

[VHDL-FPGA-Verilog] spi

Description: VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the "master" and the "slave". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.-SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the
Platform: | Size: 65536 | Author: 阿飞 | Hits:

[VHDL-FPGA-Verilog] spi

Description: SPI总线，VHDL语言，硬件描述语言源码-SPI bus, VHDL language, hardware description language source code
Platform: | Size: 3072 | Author: 郑文棋 | Hits:

[SCM] SPI

Description: // This program accesses a SPI EEPROM using polled mode access. The F06x MCU // is configured in 4-wire Single Master Mode, and the EEPROM is the only // slave device connected to the SPI bus. The read/write operations are // tailored to access a Microchip 4 kB EEPROM 25LC320. The relevant hardware // connections of the F06x MCU are shown here:
Platform: | Size: 72704 | Author: 蓝天 | Hits:

[Embeded-SCM Develop] vhdlthreelinespi

Description: ＳＰＩ总线与ＣＰＬＤ之间的通信程序，可实现ＳＰＩ串行输入，通过移位寄存器后并行输出-SPI bus and the CPLD communication between these procedures is to realize SPI serial input, through the shift register parallel output after
Platform: | Size: 1024 | Author: 金臻炜 | Hits:

[Compress-Decompress algrithms] masterspiverilog

Description: spi总线控制器的fpga实现 verilog源代码及测试-spi bus controller realize the FPGA Verilog source code and test
Platform: | Size: 180224 | Author: sang | Hits:

[SCM] ad7705

Description: adc ， ad7705 模拟spi总线的keil c51 程序，经过调试通过。-adc, ad7705 analog spi bus keil c51 procedures, after debugging through.
Platform: | Size: 2048 | Author: wlcwlc66 | Hits:

[VHDL-FPGA-Verilog] vspi

Description: spi总线控制器，包含vhdl和verilog两种代码方式来实现。-spi bus controller, including VHDL and Verilog code in two ways to achieve.
Platform: | Size: 13312 | Author: wangdong | Hits:

[VHDL-FPGA-Verilog] SPIBusVerilog

Description: SPI串行总线接口的Verilog实现，详细讲解实现过程。-SPI serial bus interface Verilog realization elaborate on the realization of the process.
Platform: | Size: 398336 | Author: zhlm88 | Hits:

[VHDL-FPGA-Verilog] SPItoVHDL

Description: VHDL语言编写的 SPI总线控制器-VHDL language ah SPI bus controller. .
Platform: | Size: 339968 | Author: 王鹏 | Hits:

[VHDL-FPGA-Verilog] 61EDA_D954

Description: 用FPGA实现的ADC采样器,用vhdl编写，spi总线-FPGA implementation using the ADC sampler, prepared using VHDL, spi bus
Platform: | Size: 58368 | Author: nbm | Hits:

[Embeded-SCM Develop] FREQSYN

Description: 使用Verilog语言编写的使用SPI总线设置频率LM2346,可通过设置其R寄存器对其输出频率进行设置（需相应的射频电路相配合）。-The use of Verilog language use SPI bus frequency settings LM2346, can be by setting up its R register set of its output frequency (to be matched by corresponding RF circuitry).
Platform: | Size: 1024 | Author: 张键 | Hits:

[Embeded-SCM Develop] EE-340_rev1

Description: SPI Bus protocol. Describes the protocol briefly with examples
Platform: | Size: 186368 | Author: manav | Hits:

[VHDL-FPGA-Verilog] LPC2DDR2

Description: Module Function Description: This module allows a SPI ROM to be used in a LX/CS5536 system. Details are below: 1.Provide a memory window to the SPI EPROM at FFF80000h-FFFFFFFFh (512KB). 2.Provide an interface to the SPI bus to allow the SPI EPROM to be programmed. 3.Support DDR2 memory initial process. 4.Support LPC/SPI ROM switch using Hardware pin selection and Software setting method 5.Support LPC Memory Read/Write, LPC I/O Read/Write 6.Support SPI Chip Erase/Byte Program/Write Status/Read Status/Read Array -Module Function Description: This module allows a SPI ROM to be used in a LX/CS5536 system. Details are below: 1.Provide a memory window to the SPI EPROM at FFF80000h-FFFFFFFFh (512KB). 2.Provide an interface to the SPI bus to allow the SPI EPROM to be programmed. 3.Support DDR2 memory initial process. 4.Support LPC/SPI ROM switch using Hardware pin selection and Software setting method 5.Support LPC Memory Read/Write, LPC I/O Read/Write 6.Support SPI Chip Erase/Byte Program/Write Status/Read Status/Read Array
Platform: | Size: 8192 | Author: 吴羽中 | Hits:

[VHDL-FPGA-Verilog] Nios_II_SPI

Description: 本源码为Nios II的开发示例,主要演示Nios II的SPI总线设计。开发环境QuartusII。 本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of an example, the main demonstration Nios II design of the SPI bus. Development environment QuartusII. This example is very classic, FPGA-based SOPC development of great help for beginners.
Platform: | Size: 16035840 | Author: huangshengqun | Hits:

[Embeded-SCM Develop] SPI_TEST

Description: The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link standard named by Motorola that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select (chip select) lines. Sometimes SPI is called a "four wire" serial bus, contrasting with three, two, and one wire serial buses.-The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link standard named by Motorola that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select (chip select) lines. Sometimes SPI is called a "four wire" serial bus, contrasting with three, two, and one wire serial buses.
Platform: | Size: 478208 | Author: wei | Hits:
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