Search - sram spartan

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[Other resource] System09 DL : 0: BurchED B5-X300 Spartan2e using XC2S300e device Top level file for 6809 compatible system on a chip Designed with Xilinx XC2S300e Spartan 2+ FPGA. Implemented With BurchED B5-X300 FPGA board, B5-SRAM module, B5-CF module and B5-FPGA-CPU-IO module-BurchED B5 - X300 Spartan2e using XC2S300e Top level device file for 6809 compatible syste m on a chip Designed with Xilinx XC2S300e Sparta n 2 FPGA. Implemented With BurchED B5 - X300 FPGA board, B5-SRAM module, B5-CF module and B5 - FPGA-CPU-IO module
Update : 2008-10-13 Size : 596.35kb Publisher : 陈朋
[VHDL-FPGA-Verilog] System09 DL : 0: BurchED B5-X300 Spartan2e using XC2S300e device Top level file for 6809 compatible system on a chip Designed with Xilinx XC2S300e Spartan 2+ FPGA. Implemented With BurchED B5-X300 FPGA board, B5-SRAM module, B5-CF module and B5-FPGA-CPU-IO module-BurchED B5- X300 Spartan2e using XC2S300e Top level device file for 6809 compatible syste m on a chip Designed with Xilinx XC2S300e Sparta n 2 FPGA. Implemented With BurchED B5- X300 FPGA board, B5-SRAM module, B5-CF module and B5- FPGA-CPU-IO module
Update : 2025-02-17 Size : 596kb Publisher : 陈朋
[VHDL-FPGA-Verilog] IS61WV51216BLL DL : 0: 备注：使用的是VeriLog HDL语言软件环境xilinx ISE 10.1，硬件：高教仪EXCD-1FPGA电路板。FPGA信号：spartan-3e . 功能编写硬件描述性语言实现FPGA对板上外设SRAM IS61WV51216BLL的读写，通过串口发送到上位机上，使用串口助手显示读取的数据。-Note: Use the VeriLog HDL language software environment xilinx ISE 10.1, hardware: Higher Miriam EXCD-1FPGA circuit boards. FPGA Signal: spartan-3e. Write functional hardware description language implementation of on-board peripherals SRAM IS61WV51216BLL FPGA to read and write, sent to the host computer through the serial port, use the serial Assistant displays the data read.
Update : 2025-02-17 Size : 5kb Publisher : 李钿
[VHDL-FPGA-Verilog] SRAM DL : 0: 使用Verilog语言编写的SRAM读写程序,不用添加IP核,在Xilinx Spartan-6上运行通过,是很好的Verlog程序-SRAM using Verilog language literacy program, do not add the IP core in Xilinx Spartan-6 run through, is a very good program Verlog
Update : 2025-02-17 Size : 9kb Publisher : 于洋
[VHDL-FPGA-Verilog] ring_fifo DL : 0: use Sram with ring fifo Spartan-3
Update : 2025-02-17 Size : 3.05mb Publisher : lee