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Description: 基于srt-2算法，利用verilog实现16位定点无符号数除法器（除数、被除数均由16位整数和16位小数组成，商由32位整数和16位小数构成，余数由32位小数组成）
Platform: |
Size: 2933 |
Author: 刘蒲霞 |
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Description: 这是一个用verilog实现的除法器代码。-This is a realization of the use verilog divider code.
Platform: |
Size: 1024 |
Author: arban |
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Description: 基于srt-2算法，利用verilog实现16位定点无符号数除法器（除数、被除数均由16位整数和16位小数组成，商由32位整数和16位小数构成，余数由32位小数组成）-Based on the srt-2 algorithm, the use of Verilog to achieve 16-bit unsigned fixed-point divider number (divisor, dividend by 16-bit integer and 16 fractional composition operators from 32-bit integer and 16 fractional composition, the remainder by 32 small array into)
Platform: |
Size: 3072 |
Author: 刘蒲霞 |
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Description: verilog code
radix-2 SRT divider
input [7:0]Dividend
input [3:0]Divisor
output [4:0]Quotient
output [8:0]Remainder
-verilog coderadix-2 SRT dividerinput [7:0] Dividend input [3:0] Divisor output [4:0] Quotient output [8:0] Remainder
Platform: |
Size: 2048 |
Author: 沙嗲 |
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Description: 基于srt-2算法，利用verilog实现16位定点无符号数除法器（除数、被除数均由16位整数和16位小数组成，商由32位整数和16位小数构成，余数由32位小数组成）-Based on srt-2 algorithm, using verilog to achieve 16-bit fixed-point unsigned divider (divisor, dividend by 16-bit integer and 16-bit decimal form, business from the 32-bit integer and 16-bit fractional composition, I composed a few from the 32-bit decimal)
Platform: |
Size: 3072 |
Author: wfwef |
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