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[VHDL-FPGA-Verilog] 数字电子钟

Description: 数字电子钟 此数字电子钟具有的功能包括： 1. 计时，时、分、秒显示； 2. 十二小时与二十四小时之间的转换； 3. 上下午显示； 4. 对时、分、秒的校时功能； 5. 跑表功能。-digital electronic clock this digital electronic clock with functions include : 1. Time, hours, minutes and seconds display; 2. 12 hours with 24 hours of conversion; 3. On the afternoon show; 4. Right hours, minutes, and seconds school function; 5. Stopwatch functions .
Platform: | Size: 7168 | Author: 吴健宇 | Hits:

[matlab] EDA_miaobiao

Description: 《数字电路EDA入门－VHDL程序实例》---数字秒表程序例子-"digital circuit EDA portal-VHDL program examples"-- digital stopwatch procedures example
Platform: | Size: 1024 | Author: 张文 | Hits:

[VHDL-FPGA-Verilog] byvhdstopwatchl

Description: 1.高精度数字秒表（0.01秒的vhdl语言实现） 2.具有定时，暂停，按键随机存储，翻页回放功能； 3.对30M时钟分频产生显示扫描时钟 4.精度高达0.01s,并且可以通过改变主频来更改分频比和记数间隔，可控性高。 5.模块化设计，其中的许多函数可以成为vhdl语言的通用经典例子（包含分频电路设计，动态扫描时钟设计，译码电路设计，存储器设计，存储回放显示设计）-1. High-precision digital stopwatch (0.01 seconds vhdl language) 2. With a timer, suspended Random memory keys, flip playback function; 3. right 30M clock frequency scan have revealed four clock. Precision high 0.01s and and can be changed to alter the frequency than the frequency interval and Hutchison, controlled high. 5. Modular design, Many of these functions can become the common language vhdl classic examples (including sub-frequency circuit design, Dynamic scanning clock design, decoding circuit design, memory design, storage intervals showed Design)
Platform: | Size: 2048 | Author: 方周 | Hits:

[File Format] VHDLEXAMPLEppt

Description: 介绍8位加法器、分频电路、数字秒表的PPT，带源码，解释详细，一步一步学习，是学习VHDL的好-introduced eight Adder, the frequency divider circuit, digital stopwatch, the PPT, with the source code, explained in detail, step by step, learning, VHDL is a good learning Eastern
Platform: | Size: 527360 | Author: 刘一 | Hits:

[Documents] VHDL

Description: VHD设计实例8位加法器的设计分频电路数字秒表的设计-VHD Design 8 adder design of sub-frequency circuit design of digital stopwatch
Platform: | Size: 569344 | Author: yyy | Hits:

[Software Engineering] clock

Description: 基于vhdl的数字钟 有闹钟,秒表,时钟,日期等功能 秒表可以开始,暂停,清零, 时钟可以设置时间, 还可以设置日期-VHDL based on the digital clock has an alarm clock, stopwatch, clock, date, stopwatch functions can start, pause, cleared, the clock can be set-up times, you can set the date
Platform: | Size: 3072 | Author: 张廷 | Hits:

[Other] C2

Description: 功能更加完善的基于vhdl的数字时钟设计 有秒表，时钟，时期，闹钟的功能和整点报时，时间调整，日期调整，闹钟的设定 、、、、、、、 秒表有开始，暂停，清零等功能，且只有在暂停的情况下才能清零。-Function more complete VHDL-based design of the digital clock stopwatch, clock, time, alarm clock function and the whole point timekeeping, time adjustment, date, alarm clock settings ,,,,,,, stopwatch has started, pause, Clear and other functions, and only in the case of the suspension can be cleared.
Platform: | Size: 817152 | Author: 张廷 | Hits:

[assembly language] dig-clock

Description: 数字钟，定时亮灯，可作秒表，有年月日显示-Digital clock, timing lights, can be used for stopwatch, date display has
Platform: | Size: 19442688 | Author: 钱慕君 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 数字秒表的设计，reset为归零设置，start为重新计时设置-Design of digital stopwatch, reset to zero settings, start time set for the re-
Platform: | Size: 309248 | Author: zhang | Hits:

[Software Engineering] digitalclockbasedoFPGA

Description: 有时间显示与设置、秒表、闹钟、日期显示与设置功能，用6个数码管显示。 -Has the time display and settings, stopwatch, alarm clock, date display and setting function, using six digital tube display.
Platform: | Size: 211968 | Author: 卓义伟 | Hits:

[VHDL-FPGA-Verilog] wtut_ver

Description: verilog HDL语言编写的数字秒表，仿真已经通过，可供参考-verilog HDL language digital stopwatch, simulation has already been adopted, for reference
Platform: | Size: 26624 | Author: 邢继元 | Hits:

[VHDL-FPGA-Verilog] multifunction_digital_clock_based_on_fpga

Description: 基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码，其功能主要有：时间设置，时间显示，跑表，分频，日期设置，日期显示等-FPGA-based multi-functional Digital Clock Design and Implementation of typhoons and rainstorms are detailed Verilog HDL source code, its functions include: time settings, time display, stopwatch, frequency, date setting, date display
Platform: | Size: 3293184 | Author: | Hits:

[Other] CLOCK

Description: 文通过ALTERA公司的quartus II软件，用Verilog HDL语言完成多功能数字钟的设计。主要完成的功能为：计时功能，24小时制计时显示；通过七段数码管动态显示时间；校时设置功能，可分别设置时、分、秒；跑表的启动、停止 、保持显示和清除。-Through the ALTERA company quartus II software, using Verilog HDL language to complete the design of multi-function digital clock. The main function of the completion are: time function, 24-hour time display through the Seven-Segment LED dynamic display time school settings function, can be set hours, minutes, seconds the stopwatch to start, stop, and maintain display and removal.
Platform: | Size: 182272 | Author: 张保平 | Hits:

[VHDL-FPGA-Verilog] paobiao

Description: 一个基于FPGA的数字跑表系统的设计，最小单位是百分表位。采用十进制进位。-FPGA-based digital stopwatch system design, the smallest unit is a digital dial indicator. Binary using the metric system.
Platform: | Size: 44032 | Author: jyb | Hits:

[VHDL-FPGA-Verilog] stopwatch

Description: 基于vhdl的数字秒表，计时精度为1/100秒，最长计时时间为59分59.59秒；设有复位开关、起停开关；验证可用。-On vhdl digital stopwatch, timing accuracy of 1/100 seconds, the longest time time of 59 minutes 59.59 seconds with reset switch, start-stop switches validation is available.
Platform: | Size: 266240 | Author: ly | Hits:

[VHDL-FPGA-Verilog] stopwatch

Description: 数字秒表的VHDL代码。当设计文件加载到目标器件后，设计的数字秒表从00-00-00开始计秒。，直到按下停止按键（按键开关S2）。数码管停止计秒。按下开始按键（按键开关S1），数码管继续进行计秒。按下复位按键（核心板上复位键）秒表从00-00-00重新开始计秒。-The VHDL code for digital stopwatch. When the design document loaded into the target device, the designed digital stopwatch count the seconds from the 00-00-00. Until you press stop key (key switch S2). Nixie tube stop count seconds. Press the start button (key switch S1), the digital control continue to count seconds. Press the reset button (core panel reset button) to restart the stopwatch count seconds from the 00-00-00.
Platform: | Size: 1024 | Author: 王唐小菲 | Hits:

[Other] shuzimiaobiaoVHDL

Description: 数字秒表的VHDL语言实现，由于系统定时器8253每秒中断18.2次,利用INT 1AH/00H取得中断次数(DX),得到54.945ms的定时单位。 -Digital stopwatch the VHDL language, because the system timer interrupt 18.2 times per second, 8253, made use of INT 1AH/00H interrupt number (DX), by 54.945ms timing unit.
Platform: | Size: 4096 | Author: 田有林 | Hits:

[VHDL-FPGA-Verilog] Digital-stopwatch-design

Description: 数字秒表的设计报告，用VHDL语言编写程序，实现分析讨论中各种功能，分别进行编译并生成相应的模块，然后将这些模块连接起来形成电路图，并进行编译、仿真。-Digital stopwatch design reports, using VHDL language programming, analysis and discussion of various functions to achieve, respectively, to compile and generate the corresponding module, and then connect these modules together to form a circuit, and compiled simulation.
Platform: | Size: 375808 | Author: 吴亮 | Hits:

[VHDL-FPGA-Verilog] Digital-stopwatch

Description: 数字秒表，用VHDL语言描述，用层次设计概念，将设计任务分成七个子模块，规定每一模块的功能和各模块之间的接口，然后再将各模块合起来形成顶层文件联试。-Digital stopwatch, using VHDL description, level design concept, the design task is divided into seven sub-module to provide the interface between each module functions and modules, then the modules together to form a top-level file joint trial.
Platform: | Size: 200704 | Author: 黄玲 | Hits:

[MiddleWare] 数字跑表VHDL

Description: 基于VHDL 实现1小时的数字跑表，包含计数器、数据存储等部分(VHDL realization of digital stopwatch based on 1 hours, including counter, data storage etc.)
Platform: | Size: 15360 | Author: zaylee | Hits:
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