Search - stopwatch quartus

[Other] 2

Description: 89c51实现电子秒表设计的电路图与源程序-89C51 electronic stopwatch design schematics and source code
Platform: | Size: 178176 | Author: 包书伟 | Hits:

[Home Personal application] digtalclk

Description: 用Altera公司的QuartusII编写的电子钟程序，可以下载至开发板，实现一个智能数字钟功能，计时，校时，闹钟，跑表等功能，也可用于学习verilog HDL语言与数字逻辑-Using Altera s QuartusII procedures for the preparation of electronic bell, you can download to a development board, the realization of an intelligent digital clock function, time, school time, alarm clock, stopwatch functions can also be used to study verilog HDL language and digital logic
Platform: | Size: 2094080 | Author: 张欢 | Hits:

[VHDL-FPGA-Verilog] miaobiao

Description: 完整的的倒计时秒表设计（指示带闪烁）ＶＨＤＬ代码，Ｑuartus 2开发环境，Archive文件，在Ｑuartus2解压即可。-Complete countdown stopwatch design (with flashing instructions) VHDL code, Quartus 2 development environment, Archive documents, in Quartus2 can extract.
Platform: | Size: 113664 | Author: 李淡 | Hits:

[VHDL-FPGA-Verilog] stop_watch

Description: 采用Quartus2编写的电子秒表电路实现计时、暂停等功能-Quartus2 prepared using electronic stopwatch timer circuit, suspension and other functions
Platform: | Size: 349184 | Author: gz208 | Hits:

[Other Embeded program] miaobiaochengxu

Description: 利用NIOS和QUARTUS系统完成一个秒表的功能，可以实现正序和倒序显示记录的时间。-Quartus system using NIOS and complete a stopwatch function, can realize positive sequence and the reverse shows record time.
Platform: | Size: 2048 | Author: 幻婳 | Hits:

[VHDL-FPGA-Verilog] stopwatch

Description: 秒表可计时，用VHDL编译的源代码，从0.1到60秒计时，解压后直接用Quartus打开project即可-Stopwatch timer can be used to compile the VHDL source code, from 0.1 to 60 seconds from time, after extracting the direct use of Quartus can open the project
Platform: | Size: 577536 | Author: xie | Hits:

[VHDL-FPGA-Verilog] paobiao

Description: 给出了数字跑表的源代码，设计了分频模块，实现了真实的时间计数，通过这个工程的训练，能更好的了解Quartus II数字电路开发的过程。-Digital stopwatch given the source code, design the sub-frequency module, the realization of the true count of time, through this project the training, to better understand the Quartus II development of the process of digital circuits.
Platform: | Size: 237568 | Author: 张应辉 | Hits:

[Other] CLOCK

Description: 文通过ALTERA公司的quartus II软件，用Verilog HDL语言完成多功能数字钟的设计。主要完成的功能为：计时功能，24小时制计时显示；通过七段数码管动态显示时间；校时设置功能，可分别设置时、分、秒；跑表的启动、停止、保持显示和清除。-Through the ALTERA company quartus II software, using Verilog HDL language to complete the design of multi-function digital clock. The main function of the completion are: time function, 24-hour time display through the Seven-Segment LED dynamic display time school settings function, can be set hours, minutes, seconds the stopwatch to start, stop, and maintain display and removal.
Platform: | Size: 182272 | Author: 张保平 | Hits:

[VHDL-FPGA-Verilog] stopwatch

Description: Quartus II工程压缩文件，是一个典型的基于FPGA的秒表工程项目，有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based project of the stopwatch, a 50MHz frequency, counting, decoding modules. Using VHDL language.
Platform: | Size: 464896 | Author: kg21kg | Hits:

[VHDL-FPGA-Verilog] miaobiao

Description: 秒表功能，自带工程，EDA的设计平台QuartusⅡ-Stopwatch functions, bring their own works
Platform: | Size: 1589248 | Author: huliyan | Hits:

[VHDL-FPGA-Verilog] stopwatch

Description: verilog 秒表程序用quartus 编写-Verilog stopwatch ............................................................................................
Platform: | Size: 431104 | Author: icer | Hits:

[VHDL-FPGA-Verilog] miaobiao

Description: 秒表数码管显示采用verilog语言编写 Quartus II 9.0sp2 编译成功后生成的所有文件已包含-Digital display with stopwatch verilog language Quartus II 9.0sp2 successfully compiled all the files have been generated that contains
Platform: | Size: 509952 | Author: 王冠 | Hits:

[VHDL-FPGA-Verilog] Multifunction-digital-clock

Description: 在quartus平台下利用Verilogyu语言编写的多功能数字钟，数字钟有定时、调时、闹钟、秒表等功能-Quartus platform the use of Verilogyu language multifunction digital clock, digital clock timing, tone, alarm clock, stopwatch functions
Platform: | Size: 5685248 | Author: | Hits:

[VHDL-FPGA-Verilog] quartus-clock.RAR

Description: 设计FPGA电路以模拟多功能电子表的工作过程，功能如下：（1 ）数字钟，要求从00：00 ：00点计到23 ：59：59 （2）数字跑表（3 ）调整时间 (4)闹钟设置，可以设置2个闹钟，闹钟时间到了后会提醒，提醒时间持续20 秒，如果此时按A键，则该闹钟解除提醒，如果按住B键，闹钟暂停提醒。但是3 分钟后重复提醒一次。如果闹钟响时没有按键，则响完20秒之后暂停，然后同样3 分钟后重新提醒一次。（5 ）日期设置。可以设置当前的日期，比如2012年08月20 日。-Design FPGA circuits to analog the multifunctional electronic table work process, the following functions: (1) digital clock count: 00 points from 00:00 to 23: 59:59 (2) digital the stopwatch (3) to adjust the time (4 ) set the alarm clock, can set two alarm clock, alarm time to remind reminder time for 20 seconds, then press the A key, the alarm clock lifted reminder, if you hold down the B button, snooze alert. But three minutes later repeated reminder. If the alarm goes off, no buttons, sound finished 20 seconds after the pause, and then the same three minutes after the re-remind once. (5) The date is set. Can be set to the current date, such as the August 20, 2012.
Platform: | Size: 1664000 | Author: 章梓音 | Hits:

[VHDL-FPGA-Verilog] EXP6

Description: 基于Verilog 的实现秒表的程序先要安装Quartus II 6.0 可用看到时序仿真-To achieve a stopwatch program Verilog to install Quartus II 6 can be used to see the timing simulation based on
Platform: | Size: 215040 | Author: 周波 | Hits:

[VHDL-FPGA-Verilog] Timer

Description: Verilog编写的多功能秒表，Quartus仿真及硬件测试通过。-Verilog prepared by the multi-function stopwatch, Quartus simulation and hardware testing through.
Platform: | Size: 1686528 | Author: styx | Hits:

[Embeded-SCM Develop] Archive

Description: 基于QUARTUS II上的数电仿真实验，电子秒表-QUARTUS II based on the number of electrical simulation, electronic stopwatch
Platform: | Size: 1234944 | Author: 谈谈 | Hits:

[VHDL-FPGA-Verilog] zyclock

Description: 采用EDA技术，使用Quartus实现了数字秒表的设计，能跑通-Using EDA technology, the use of Quartus achieve a digital stopwatch, run through
Platform: | Size: 1417216 | Author: Zoe | Hits:

[Other Embeded program] stopwatch

Description: FPGA程序，verilog HDL语言编写的秒表程序，使用quartus II 13.0 开发，初学verilog HDL的同学可以参考下-FPGA procedures, verilog HDL language stopwatch program, developed using quartus II 13.0, verilog HDL beginner students can refer
Platform: | Size: 2949120 | Author: suchenguang | Hits:

[VHDL-FPGA-Verilog] miaobiao

Description: 秒表数码管实现，通过仿真验证，已下载到板子验证(The realization of the stopwatch digital tube)
Platform: | Size: 608256 | Author: aiwosuoai5015 | Hits:

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[Other] 2

[Home Personal application] digtalclk

[VHDL-FPGA-Verilog] miaobiao

[VHDL-FPGA-Verilog] stop_watch

[Other Embeded program] miaobiaochengxu

[VHDL-FPGA-Verilog] stopwatch

[VHDL-FPGA-Verilog] paobiao

[Other] CLOCK

[VHDL-FPGA-Verilog] stopwatch

[VHDL-FPGA-Verilog] miaobiao

[VHDL-FPGA-Verilog] stopwatch

[VHDL-FPGA-Verilog] miaobiao

[VHDL-FPGA-Verilog] Multifunction-digital-clock

[VHDL-FPGA-Verilog] quartus-clock.RAR

[VHDL-FPGA-Verilog] EXP6

[VHDL-FPGA-Verilog] Timer

[Embeded-SCM Develop] Archive

[VHDL-FPGA-Verilog] zyclock

[Other Embeded program] stopwatch

[VHDL-FPGA-Verilog] miaobiao

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