Description: VERILOG设计实例,非常详细的例子,有交通灯,频率计,数字跑表等等例子-Verilog design example, a very detailed examples have traffic lights, frequency meter, digital stopwatch, etc. Examples of Platform: |
Size: 159744 |
Author:luojinwen |
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Description: Quartus II工程压缩文件,是一个典型的基于FPGA的秒表工程项目,有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based project of the stopwatch, a 50MHz frequency, counting, decoding modules. Using VHDL language. Platform: |
Size: 464896 |
Author:kg21kg |
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Description: 用C#写的跑表,用于学习Timer控件和C#下的stopwatch类,在VS.net 2005下运行通过.-Using C# to write the stopwatch for the study and Timer controls and C# under the stopwatch class, VS.net 2005 in the run through. Platform: |
Size: 38912 |
Author:weixin |
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Description: 一个用Verilog实现的数字跑表的程序
希望对你的设计有帮助-With the realization of a digital stopwatch Verilog process of design you would like to help Platform: |
Size: 1024 |
Author:YangPeng |
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Description: The program is written in verilog to accomplish functions of a stopwatch. It can be implemented in Xilinx FPGA spartan 3 board. Platform: |
Size: 2048 |
Author:flyingwings |
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Description: 这是一个数字跑表的代码,用FPGA实现的,对大家或许有用-This is a digital stopwatch in the code, FPGA implementation, perhaps all of us Platform: |
Size: 161792 |
Author:马秀成 |
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Description: 秒表 verilog 程序非常适合刚接触 vreilog语言的人学习-Stopwatch verilog program is ideal for people new to vreilog language learning Platform: |
Size: 373760 |
Author:张江 |
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Description: 用verilog在basys2开发板上实现一个具有置零、开始、暂停、记忆功能的秒表。(Implement a stopwatch which containing reset,pause,start,memory functions with the verilog on the vivado based on the basys2 development board.) Platform: |
Size: 637952 |
Author:terriao
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