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[Embeded-SCM Developpaobiao

Description: 用verilog写的跑表程序--Stopwatch program written by verilog.
Platform: | Size: 1024 | Author: | Hits:

[OtherPAOBIAO_V

Description: 带音乐功能的跑表VerilogHDL描述-music with the stopwatch Verilog HDL description
Platform: | Size: 4096 | Author: nil | Hits:

[VHDL-FPGA-Verilogshuzimiaobiao

Description: 用verilog实现了一个数字秒表的设计-verilog achieved using a digital stopwatch Design
Platform: | Size: 1024 | Author: qihuolin | Hits:

[VHDL-FPGA-Verilogverilog

Description: VERILOG设计实例,非常详细的例子,有交通灯,频率计,数字跑表等等例子-Verilog design example, a very detailed examples have traffic lights, frequency meter, digital stopwatch, etc. Examples of
Platform: | Size: 159744 | Author: luojinwen | Hits:

[VHDL-FPGA-Verilogstopwatch

Description: Quartus II工程压缩文件,是一个典型的基于FPGA的秒表工程项目,有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based project of the stopwatch, a 50MHz frequency, counting, decoding modules. Using VHDL language.
Platform: | Size: 464896 | Author: kg21kg | Hits:

[.netStopWatch

Description: 用C#写的跑表,用于学习Timer控件和C#下的stopwatch类,在VS.net 2005下运行通过.-Using C# to write the stopwatch for the study and Timer controls and C# under the stopwatch class, VS.net 2005 in the run through.
Platform: | Size: 38912 | Author: weixin | Hits:

[VHDL-FPGA-VerilogStopWatch

Description: Verilog 编写的 秒表程序,在数码管上显示,带有清0和暂停键-Stopwatch Implemented by Verilog hdl
Platform: | Size: 584704 | Author: 洪磊 | Hits:

[VHDL-FPGA-VerilogDigitalWatchVerilog

Description: 一个用Verilog实现的数字跑表的程序 希望对你的设计有帮助-With the realization of a digital stopwatch Verilog process of design you would like to help
Platform: | Size: 1024 | Author: YangPeng | Hits:

[VHDL-FPGA-Verilogstopwatch

Description: The program is written in verilog to accomplish functions of a stopwatch. It can be implemented in Xilinx FPGA spartan 3 board.
Platform: | Size: 2048 | Author: flyingwings | Hits:

[VHDL-FPGA-Verilogwatch

Description: 基于verilog-HDL的电子秒表电路,采用quartusII72编译仿真,经下载测试通过。-Verilog-HDL-based electronic stopwatch circuit simulation using quartusII72 compiled by downloading the test.
Platform: | Size: 388096 | Author: 潘萌 | Hits:

[VHDL-FPGA-Verilogcode

Description: 这是一个数字跑表的代码,用FPGA实现的,对大家或许有用-This is a digital stopwatch in the code, FPGA implementation, perhaps all of us
Platform: | Size: 161792 | Author: 马秀成 | Hits:

[VHDL-FPGA-Verilogstopwatch

Description: verilog 秒表程序 用quartus 编写-Verilog stopwatch ............................................................................................
Platform: | Size: 431104 | Author: icer | Hits:

[VHDL-FPGA-Verilogkey_display

Description: 秒表 verilog 程序非常适合刚接触 vreilog语言的人学习-Stopwatch verilog program is ideal for people new to vreilog language learning
Platform: | Size: 373760 | Author: 张江 | Hits:

[VHDL-FPGA-Verilogstopwatch1

Description: stopwatch : verilog source code
Platform: | Size: 1125376 | Author: hanjaeyoung | Hits:

[VHDL-FPGA-Verilogstopwatch

Description: 用Verilog编写的秒表,可以实现计时、复位、暂停等功能。-stopwatch using Verilog language
Platform: | Size: 486400 | Author: 陈璜骁 | Hits:

[VHDL-FPGA-Verilog60-seconds-stopwatch--0.1S

Description: 60秒秒表设计 精确到0.1秒 有开始,有暂停 又终止-60 seconds stopwatch verilog
Platform: | Size: 4096 | Author: 董福 | Hits:

[VHDL-FPGA-Verilogstopwatch---60s

Description: 60秒stopwatch verilog语言编写 又开始位 有暂停位 有终止位-60s stopwatch verilog
Platform: | Size: 3072 | Author: 董福 | Hits:

[VHDL-FPGA-Verilogstopwatch-programmer-

Description: 秒表 stopwatch verilog语言编写-stopwatch verilog
Platform: | Size: 3072 | Author: 董福 | Hits:

[VHDL-FPGA-Verilog60s-StopWatch--verilog

Description: stopwatch 60s计数 精确到0.1秒 verilog语言编写-stopwatch verilog
Platform: | Size: 586752 | Author: 董福 | Hits:

[VHDL-FPGA-VerilogVerilog秒表设计

Description: 用verilog在basys2开发板上实现一个具有置零、开始、暂停、记忆功能的秒表。(Implement a stopwatch which containing reset,pause,start,memory functions with the verilog on the vivado based on the basys2 development board.)
Platform: | Size: 637952 | Author: terriao | Hits:
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