Search - synthesizer VHDL

[VHDL-FPGA-Verilog] DDS_sin

Description: 用VHDL语言实现DDS直接数字频率合成器的设计，采用正弦RAM表，可实现频率可控的正弦数字信号，编译、仿真通过。-VHDL DDS Direct Digital Frequency Synthesizer Design using sinusoidal RAM table achieve controllable frequency sinusoidal digital signal, compile, through simulation.
Platform: | Size: 8192 | Author: sarahyu | Hits:

[VHDL-FPGA-Verilog] EDAdesign(3)

Description: 该文件中是关于一些VHDL许多编程实例以及源码分析，希望对VHDL爱好者有用。卷3包括车载DVD位控系统、直接数字频率合成器、图像边缘检测器、等精度数字频率计、出租车计费系统的设计与分析-The document is on a number of VHDL source code in many programming examples and analysis, in the hope that useful VHDL enthusiasts. Car DVD Volume 3 includes digital control system, direct digital frequency synthesizer, image edge detector, such as precision digital frequency meter, taxi Accounting System Design and Analysis
Platform: | Size: 4392960 | Author: shengm1 | Hits:

[VHDL-FPGA-Verilog] FPGAddfs

Description: 基于FPGA的直接数字频率合成器的设计与实现.-FPGA-Based Direct Digital Frequency Synthesizer Design and Implementation.
Platform: | Size: 222208 | Author: 周真 | Hits:

[Software Engineering] pllddfs

Description: 一种基于锁相环的数字频率合成器的设计-Based on Phase-Locked Loop Digital Frequency Synthesizer Design
Platform: | Size: 111616 | Author: 周真 | Hits:

[VHDL-FPGA-Verilog] vhdlddfs

Description: 用VHDL设计直接数字频率合成器-VHDL design with direct digital frequency synthesizer
Platform: | Size: 190464 | Author: 周真 | Hits:

[Software Engineering] SW

Description: FPGA弹弓无线呼叫系统分发射和接收两大部分。发射部分采用锁相环式频率合成器技术-FPGA slingshot wireless call system transmitting and receiving at most two. Part of the launch phase-locked loop frequency synthesizer using technology
Platform: | Size: 628736 | Author: w | Hits:

[VHDL-FPGA-Verilog] dds

Description: 直接数字频率合成器，基于vhdl语言，在qartus II上实现，下载调试成功-Direct digital frequency synthesizer, based on the VHDL language, in qartus II achieved a successful download debugging
Platform: | Size: 316416 | Author: 浮云 | Hits:

[SCM] dds_quicklogic

Description: dds直接频率合成源代码，基于rom表方式-dds a direct frequency synthesizer source code, based on the way rom Table
Platform: | Size: 22528 | Author: zhangxi | Hits:

[VHDL-FPGA-Verilog] dds

Description: DDs直接数字频率合成器的源代码，其中包括采用IP核和普通两种方式-DDS Direct Digital Synthesizer source code, including the use of IP core and the general two ways
Platform: | Size: 1378304 | Author: 谭儆轩 | Hits:

[Wavelet] DDS

Description: 利用EDA技术和FPGA在UP3开发板上实现直接数字频率综合器的设计。实验中加入了相位控制字PWORD，用以控制相位偏移量的前四位，将相位偏移量加到ROM地址总线上，从而引起从ROM中取得的正弦信号的偏移，实现移相信号发生器的移相功能。实验中还加入了LCD显示功能，通过LCD显示模块器件，用LCD显示正弦信号的频率，所显示的频率也是由频率字控制的。LCD的驱动原理同上次实验。-The use of EDA technology and FPGA development in the UP3 board direct digital frequency synthesizer design. Experiment by adding a phase control word PWORD, to control the phase offset of the top four will be added to the phase offset ROM address bus, thereby causing ROM obtained from the sinusoidal signal offset, shifted believe realize its phase-shifting function generator. Experiments have also joined the LCD display, LCD display module through the device, with LCD display the frequency of sinusoidal signal, as shown by the frequency of word frequency control. LCD driving principles with the previous experiment.
Platform: | Size: 1225728 | Author: Emma | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 本文使用实例描述了在 FPGA/CPLD 上使用 VHDL 进行分频器设计，包括偶数分频、非 50％占空比和 50％占空比的奇数分频、半整数（N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可通过 Synplify Pro 或 FPGA 生产厂商的综合器进行综合，形成可使用的电路，并在 ModelSim 上进行验证。 -This article describes the use of examples in the FPGA/CPLD prescaler to use VHDL to design, including the even-numbered sub-frequency, non-50 duty cycle and 50 duty cycle of the odd-numbered sub-frequency, semi-integer (N+ 0.5) sub-frequency, fractional-N, as well as scores of sub-band frequency points. All can realize through the Synplify Pro or FPGA manufacturers integrated synthesizer to form a circuit can be used and verified in the ModelSim on.
Platform: | Size: 322560 | Author: 黄鹏曾 | Hits:

[VHDL-FPGA-Verilog] EDA

Description: 本章介绍了两个EDA技术的综合应用设计实例:数字闹钟和直接数字频率合成器DDS。-EDA chapter describes the two technologies integrated application design example: digital alarm clock and direct digital synthesizer DDS.
Platform: | Size: 181248 | Author: 黄鹏曾 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 实现数字频率合成。能产生任意频率的正弦信号、方波信号、梯形波等，并且能对信号的频率进行测量。-Digital frequency synthesizer. Can generate any frequency sinusoidal signal, square-wave signal, a trapezoidal wave, etc., and can measure the frequency of the signal.
Platform: | Size: 278528 | Author: 吴健 | Hits:

[VHDL-FPGA-Verilog] DDS_VHDL

Description: 基于FPGA的直接数字频率合成器（DDS）设计（源程序）-FPGA-based direct digital synthesizer (DDS) design (source code)
Platform: | Size: 236544 | Author: jacky | Hits:

[SCM] DDS

Description: 《DDS 原理简介》，DDS即直接数字频率合成器原理简介及系统设计与实现- DDS Principle , DDS direct digital synthesizer Principle and System Design and Implementation
Platform: | Size: 454656 | Author: 范田田 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 《DDS原理简介(中文)》DDS即直接数字频率合成器，原理及系统设计实现- DDS Principle Introduction (Chinese) DDS direct digital frequency synthesizer, the principle and system design to achieve
Platform: | Size: 454656 | Author: 范田田 | Hits:

[Software Engineering] 111

Description: 数字鉴相器,数字锁相环频率合成系统FPGA的实现,很有借鉴价值-Digital phase detector, digital PLL frequency synthesizer system FPGA realization of referential value
Platform: | Size: 53248 | Author: 颜小山 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 使用VHDL硬件描述语言实现了直接频率合成器的制作，并在Altera公司的CycloneII上得到实现，验证了代码的正确性。用户操作可以参照程序中的说明，请使用QuartusII6.0以上版本打开，低版本打开时会有错误提示-Using VHDL hardware description language to achieve a direct frequency synthesizer production, and Altera s CycloneII be realized, to verify the correctness of the code. Users can refer to procedures, please use the above QuartusII6.0 open, low-version will be opened error
Platform: | Size: 105472 | Author: xx | Hits:

[VHDL-FPGA-Verilog] FPGA-DDC

Description: 基于FPGA的直接数字频率合成器的设计和实现。-FPGA-Based Direct Digital Frequency Synthesizer Design and Implementation.
Platform: | Size: 100352 | Author: 孙新荣 | Hits:

[VHDL-FPGA-Verilog] DPLL

Description: 数字锁相环频率合成器的vhdl实现的源代码-Digital PLL Frequency Synthesizer vhdl source code to achieve
Platform: | Size: 539648 | Author: sunnyhp | Hits:

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[VHDL-FPGA-Verilog] DDS_sin

[VHDL-FPGA-Verilog] EDAdesign(3)

[VHDL-FPGA-Verilog] FPGAddfs

[Software Engineering] pllddfs

[VHDL-FPGA-Verilog] vhdlddfs

[Software Engineering] SW

[VHDL-FPGA-Verilog] dds

[SCM] dds_quicklogic

[VHDL-FPGA-Verilog] dds

[Wavelet] DDS

[VHDL-FPGA-Verilog] VHDL

[VHDL-FPGA-Verilog] EDA

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] DDS_VHDL

[SCM] DDS

[VHDL-FPGA-Verilog] DDS

[Software Engineering] 111

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] FPGA-DDC

[VHDL-FPGA-Verilog] DPLL

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