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[Embeded-SCM Develop] 148个verilog hdl小程序（有很多testbench）——

Description: 148个verilog hdl小程序（有很多testbench）——.-148 Verilog HDL small programs (many testbench) from Part
Platform: | Size: 55296 | Author: 地方 | Hits:

[Crack Hack] MD5(verilog)

Description: MD5算法的verilog实现，同时包含有testbench。-Verilog of MD5 algorithm is realized, includes testbench at the same time .
Platform: | Size: 4096 | Author: 张雷 | Hits:

Description: Verilog的学习资料，可编程器件fpga的开发语言，有重点介绍Verilog的关键语法-Verilog learning materials, they simply PLD development language, and to highlight the key Verilog syntax
Platform: | Size: 468992 | Author: 张 | Hits:

[VHDL-FPGA-Verilog] Verilog HDL设计练习进阶

Description: 初学verilog HDL时找的好资料大家共享-Beginners should try to find a good share information
Platform: | Size: 680960 | Author: chencsw | Hits:

[VHDL-FPGA-Verilog] sram

Description: sram 读写小程序，用verilog编写的，请各位高手指教-SRAM read and write small programs using Verilog prepared, please enlighten you master
Platform: | Size: 1024 | Author: kevin | Hits:

[VHDL-FPGA-Verilog] ADPLL

Description: verilog ADPLL file with testbench.v
Platform: | Size: 25600 | Author: | Hits:

[Embeded-SCM Develop] 16bit_booth_multiplier_STG

Description: verilog程序，实现两个16bit数乘法，采用booth算法，基于状态机实现，分层次为datapath和controller两个子模块，testBench测试通过-verilog procedures, two 16bit multiplication, the algorithm used booth. Based on the state machine achieved at different levels for datapath controller and two sub-modules, testBench the test
Platform: | Size: 2048 | Author: | Hits:

[File Format] verilog_testbench_preliminary

Description: verilog testbench preliminary，很有用的-verilog testbench preliminary, very useful
Platform: | Size: 60416 | Author: 刘彦 | Hits:

[VHDL-FPGA-Verilog] oc8051

Description: 8051的verilog实现，内附testbench,c语言调试程序-8051 verilog achieve, enclosing testbench, c language debugging procedures
Platform: | Size: 1226752 | Author: wutailiang | Hits:

[Other Embeded program] FIFO_v

Description: FIFO的verilog实现，内附testbench和文档说明-FIFO verilog achieve, enclosing testbench and documentation shows
Platform: | Size: 175104 | Author: wutailiang | Hits:

[VHDL-FPGA-Verilog] s_fifo

Description: 一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.两种方式,包含testbench-Verilog language describes a synchronous fifo, including: Fifo using declared registers for storage and Fifo using (model of) standard memory chip for storage. In two ways, including Testbench
Platform: | Size: 2048 | Author: 彭帅 | Hits:

[VHDL-FPGA-Verilog] dac

Description: DAC converter design with Verilog code and testbench
Platform: | Size: 527360 | Author: 田磊 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 一个桶形移位寄存器的.v文件，含testbench-Shift Registers a bucket. V file containing Testbench
Platform: | Size: 1024 | Author: QU YIFAN | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 一个简单状态机的.v文件，含testbench-A simple state machine. V file containing Testbench
Platform: | Size: 1024 | Author: QU YIFAN | Hits:

[VHDL-FPGA-Verilog] crc16_ccitt

Description: crc_table.c is for reset seed( 0000 ) crc_table_1.c is for reset seed( ffff) CRC16_D8_m.v is a verilog module of byte paralle crc. CRC16_D8_m_tb.v is the testbench file of above module. -crc_table.c is for reset seed (0000) crc_table_1.c is for reset seed (ffff) CRC16_D8_m.v is a verilog module of byte paralle crc.CRC16_D8_m_tb.v is the testbench file of above module.
Platform: | Size: 3072 | Author: 樊文杰 | Hits:

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[Embeded-SCM Develop] 148个verilog hdl小程序（有很多testbench）——

[Crack Hack] MD5(verilog)

[Other] 《Verilog黄金指南》中文翻译版

[VHDL-FPGA-Verilog] Verilog HDL设计练习进阶

[VHDL-FPGA-Verilog] sram

[VHDL-FPGA-Verilog] ADPLL

[Embeded-SCM Develop] 16bit_booth_multiplier_STG

[File Format] verilog_testbench_preliminary

[VHDL-FPGA-Verilog] oc8051

[Other Embeded program] FIFO_v

[VHDL-FPGA-Verilog] s_fifo

[VHDL-FPGA-Verilog] dac

[VHDL-FPGA-Verilog] verilog

[VHDL-FPGA-Verilog] verilog

[VHDL-FPGA-Verilog] crc16_ccitt

[VHDL-FPGA-Verilog] Models_and_Testbenches_11_10_2004

[VHDL-FPGA-Verilog] SPI_FireWall

[Windows CE] wince+spi

[VHDL-FPGA-Verilog] Testbench(Verilog)

[VHDL-FPGA-Verilog] testbench

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