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Description: 6位LED电子钟,非常实用实做过实验，自动报时，秒表-6 LED electronic clock, very useful experiment is done, automatic timer, stopwatch. . .
Platform: |
Size: 4096 |
Author: 王睿 |
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Description: 实验采用七段码LED设计（数码管），显示直观；采用定时器中断，计时更准确；功能齐全，可随时启动、停止、清零，后者智能化程度更高。-Seven-Segment LED code using the experimental design (digital control), visual display using timer interrupt, a more accurate time functions, may at any time to start, stop, cleared, and the latter an even higher degree of intelligence.
Platform: |
Size: 33792 |
Author: cuipinpin |
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Description: 用VHDL语言设计一个数字秒表：
1、 秒表的计时范围是0秒~59分59.99秒，显示的最长时间为59分59秒。
2、 计时精度为10MS。
3、 复位开关可以随时使用，按下一次复位开关，计时器清零。
4、 具有开始/停止功能，按一下开关，计时器开始计时，再按一下，停止计时。系统设计分为几大部分，包括控制模块、时基分频模块、计时模块和显示模块等。其中，计时模块有分为六进制和十进制计时器。计时是对标准时钟脉冲计数。计数器由四个十进制计数器和两个六进制计数器构成，其中毫秒位、十毫秒位、秒位和分位用十进制计数器，十秒位和十分位用六进制计数器。计时显示电路时将计时值在LED上七段数码管上显示出来。计时电路产生的计时值经过BCD七段码后，驱动LED数码管。-With VHDL language design digit stopwatch: 1, Stopwatch s time scope is 0 second ~59 minute 59.99 second, the demonstration longest time is 59 minute 59 second. 2, The time precision is 10MS. 3, The reset switch may momentarily use, presses down a reset switch, the timer reset. 4, Has starts/the stop function, according to the switch, the timer starts to time, presses again, stops timing. The system design divides into several major parts, including control module, time base frequency division module, time module and display module and so on. And, the time module influentials for the senary and the decimal base timer. The time is to the standard clock pulse counting. Counter by four decade counters and two senary counter constitution, a millisecond position, ten milliseconds positions, a second position and the rank with the decade counter, ten second position and ten ranks use the senary counter. When time display circuit will time the value on the nixietube to demonstrate on LED. The
Platform: |
Size: 5120 |
Author: SAM |
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Description: 实现定时器功能，分别有秒针，分钟，小时，到一天后led灯闪烁一下。-To achieve timer function, respectively, seconds, minutes, hours, to one day look after the led light flashes.
Platform: |
Size: 1024 |
Author: crystal |
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Description: 调用总共四个计数器（两个六进制，两个十进制，六进制计数器可由实验五的程序做简单修改而成）串起来构成异步计数器，计数器的值，通过实验九串行扫描输出。用1Hz连续脉冲作为输入，这样就构成一个简单的1h计时器。带一个清零端。
输入：连续脉冲，逻辑开关；输出：七段LED。
-Called a total of four counters (two six-band, two decimal, hexadecimal counter by six experimental procedure to do five simple changes made) string together to form an asynchronous counter, the counter, and by nine serial scan test output. 1Hz pulse with a continuous input, it constitutes a simple timer 1h. With a clear end. Input: Continuous pulse, logic switches output: seven-segment LED.
Platform: |
Size: 6144 |
Author: 李小勇 |
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Description: 定时器中断的例程，实现一秒定时，并在led灯上显示- Writes routine which a timer interrupts, realizes one second fixed time, and demonstrated on the led lamp
Platform: |
Size: 3072 |
Author: 蔡林 |
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Description: FPGA做的电子钟，通过定时器实现。用vhdl做的led ip核，软件实现控制显示-FPGA do electronic bell, by timer implementation. Led ip vhdl do with nuclear, software control display
Platform: |
Size: 14768128 |
Author: 勇磊 |
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Description: 设计一个多功能数字钟，要求显示格式为小时－分钟－秒钟，整点报时，报时时间为10 秒，即从整点前10 秒钟开始进行报时提示，喇叭开始发声，直到过整点时，在整点前5 秒LED 开始闪烁，过整点后，停止闪烁。系统时钟选择时钟模块的10KHz，要得到1Hz 时钟信号，必须对系统时钟进行10,000次分频。调整时间的的按键用按键模块的S1 和S2，S1 调节小时，每按下一次，小时增加一个小时，S2 调整分钟，每按下一次，分钟增加一分钟。另外用S8 按键作为系统时钟复位，复位后全部显示00－00－00。-The design of a multi-function digital clock, required to display format for hours: Minutes: seconds, the whole point timekeeping and timer for 10 seconds, namely the whole point of 10 seconds before start timekeeping prompt, horn began to sound, until the whole point, in the whole point of 5 seconds the LED flashes, over the whole point, stop flicker. System clock to the clock module 10KHz, to get the 1Hz clock signal, the system must be 10000 times the system clock. Adjust the time of the keys with the key module S1 and S2, S1 adjust the hours, each press once, an hour to increase an hour, S2 to adjust the minutes, every time you press a minute, a minute. We also use the S8 button as the system clock reset, reset all display 00-00-00.
Platform: |
Size: 7658496 |
Author: 冯雨娴 |
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Description: 用VHDL 语言设计数字钟，实现在数码管上显示分钟和秒，并且可以手动调节分钟，
实现分钟的增或者减。该设计包括以下几个部分：
（1）分频电路的设计，产生1Hz 的时钟信号，作为秒计时脉冲；
（2）手动调节电路，包括“时增”“时减”“分增”“分减”。
（3）时分秒计时电路。
（4）7 段数码管显示电路。
将 SW1 和SW2 初始状态均置为高电平。拨动开关SW1 到低，分钟进行加计数，秒停
止计数，当计数到59 时，从00 开始重新加计数，将SW1 拨动到高时，在当前状态进行计时。当拨动开关SW2 为低时，分钟进行减计数，秒停止计数，当减到0 时，从59 开始减计数，将SW2 拨动到高时，在当前状态进行计时。-VHDL language with the design of digital clock, in the digital display minutes and seconds, and can manually adjust the minutes,
To achieve the increase or decrease minutes. The design includes the following sections:
(1) frequency circuit design, resulting in 1Hz clock signal, as the second time pulse
(2) manual adjustment of the circuit, including when the increase when the minus points by sub-minus.
(3) when the minutes and seconds timer circuit.
(4) 7-segment LED display circuit.
Set the initial state of SW1 and SW2 to high level. Toggle switch SW1 to low, minute to count up, seconds to stop
Stop counting, when counting to 59, 00 to re-count the start, will SW1 toggle to high, in the current state of time. When the switch SW2 is low, the timer counts down in minutes and stops counting in seconds. When it decreases to 0, it counts down 59, and turns SW2 to HIGH to count in the current state.
Platform: |
Size: 495616 |
Author: panda |
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