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[Other resource] vhdl--timer

Description: 关于基于fpga的，数字化时钟vhdl实现源程序，推荐大家下载仿真实现。
Platform: | Size: 6262 | Author: sxd | Hits:

[Other resource] VHDL-timer

Description: 这是关于VHDL时钟的源代码，欢迎大家下载交流！
Platform: | Size: 6967 | Author: 张三 | Hits:

[VHDL-FPGA-Verilog] 多功能电子钟

Description: 具有多种功能的电子钟：闹钟，报时和修改，定时闹钟，报时时间，带闹钟，报时开关。-with multiple functions of electronic bell : alarm clock, timer and modification, regular alarm clock, timer, with alarm clock, timer switches.
Platform: | Size: 6144 | Author: 张建 | Hits:

[VHDL-FPGA-Verilog] vhdl--timer

Description: 关于基于fpga的，数字化时钟vhdl实现源程序，推荐大家下载仿真实现。-On the FPGA-based, digital clock source VHDL realize recommend everyone to download simulation.
Platform: | Size: 6144 | Author: sxd | Hits:

[ARM-PowerPC-ColdFire-MIPS] VHDL-timer

Description: 这是关于VHDL时钟的源代码，欢迎大家下载交流！-This is a clock on the VHDL source code, welcomed the exchange of everyone to download!
Platform: | Size: 7168 | Author: 张三 | Hits:

[VHDL-FPGA-Verilog] stop_watch

Description: 采用Quartus2编写的电子秒表电路 实现计时、暂停等功能-Quartus2 prepared using electronic stopwatch timer circuit, suspension and other functions
Platform: | Size: 349184 | Author: gz208 | Hits:

[Software Engineering] CPLD-timer

Description: 本文介绍一种以CPLD[1]为核心、以VHDL[2]为开发工具的时间控制器，该控制器不仅具有时间功能，而且具有定时器功能，能在00：00～23：59之间任意设定开启时间和关闭时间，其设置方便、灵活，广泛应用于路灯、广告灯箱、霓虹灯等处的定时控制。-This article describes a CPLD [1] as the core, VHDL [2] for the development of tools for time controller that features not only has the time, but with the timer function, can be between 00:00 ~ 23:59 arbitrarily set to open time and closing time, and its convenient, flexible, widely used in street lamps, advertising light boxes, neon lights, etc. The timing control.
Platform: | Size: 219136 | Author: 江俊 | Hits:

[VHDL-FPGA-Verilog] timer

Description: vhdl代码：电子时钟VHDL程序与仿真！初学fpga者可以参考参考！！比较简单-VHDL code: electronic clock and simulation of VHDL procedures! FPGA beginner who can refer to reference! ! Relatively simple
Platform: | Size: 59392 | Author: daxiadian2 | Hits:

[VHDL-FPGA-Verilog] 8253

Description: With realize based on the FPGA programmable timer counter 8253 designs -With realize based on the FPGA programmable timer counter 8253 designs
Platform: | Size: 7168 | Author: 靖书磊 | Hits:

[VHDL-FPGA-Verilog] timer

Description: VHDL语言设计的数字钟 具有时分秒三段显示-VHDL language designed with time-accurate digital clock shows three paragraphs
Platform: | Size: 1024 | Author: 孙明 | Hits:

[VHDL-FPGA-Verilog] timer

Description: 淺顯易懂的學習verilog程式基礎範例以時鐘為示範-Learn easy to understand the basic Verilog code for an example of a clock model
Platform: | Size: 1024 | Author: 劉季泓 | Hits:

[Documents] vhdl

Description: 6位LED电子钟,非常实用实做过实验，自动报时，秒表-6 LED electronic clock, very useful experiment is done, automatic timer, stopwatch. . .
Platform: | Size: 4096 | Author: 王睿 | Hits:

[SCM] miaobiao.RAR

Description: 实验采用七段码LED设计（数码管），显示直观；采用定时器中断，计时更准确；功能齐全，可随时启动、停止、清零，后者智能化程度更高。-Seven-Segment LED code using the experimental design (digital control), visual display using timer interrupt, a more accurate time functions, may at any time to start, stop, cleared, and the latter an even higher degree of intelligence.
Platform: | Size: 33792 | Author: cuipinpin | Hits:

[VHDL-FPGA-Verilog] Timer

Description: ep2c5 实现 定时器 verilog语言，quartus 2 仿真-verilog language to achieve ep2c5 timer, quartus 2 Simulation
Platform: | Size: 497664 | Author: lizhuodong | Hits:

[Windows Develop] jishiqi

Description: 24小时计时器，本计时器能够实现时分秒的精确计时(测试可用)-24-hour timer, the timer to achieve the precise time when minutes and seconds (test available)
Platform: | Size: 2048 | Author: matao | Hits:

[VHDL-FPGA-Verilog] timer

Description: 计时器的Verilog描述 CPU设计者可以借鉴 -Verilog decription of the timer in processors
Platform: | Size: 2048 | Author: Dee | Hits:

[Internet-Network] timer

Description: AHDL parametrized timer - for Altera Quartus compiler only-AHDL parametrized timer- for Altera Quartus compiler only
Platform: | Size: 1024 | Author: kkris | Hits:

[VHDL-FPGA-Verilog] FPGA_Clk

Description: 基于Cyclone EP1C6240C8 FPGA的时钟产生模块。主要用于为FPGA系统其他模块产生时钟信号。采用verilog编写。 使用计时器的方式产生时钟波形。 提供对于FPGA时钟的偶数分频、奇数分频、始终脉冲宽度等功能。-Based on Cyclone EP1C6240C8 FPGA' s clock generator module. Is mainly used for the FPGA system clock signal generated in other modules. The use of the timer-generated clock waveform. To provide for the FPGA clock even sub-frequency, odd-numbered sub-frequency, pulse width is always functions.
Platform: | Size: 1466368 | Author: icemoon1987 | Hits:

[Documents] top

Description: 实现定时器功能，分别有秒针，分钟，小时，到一天后led灯闪烁一下。-To achieve timer function, respectively, seconds, minutes, hours, to one day look after the led light flashes.
Platform: | Size: 1024 | Author: crystal | Hits:

[VHDL-FPGA-Verilog] timer

Description: 外设timer设计：16bit定时器、ETU计数器、具有3种可配置中断请求输出、内部寄存器的读写编程。-Peripheral timer design: 16bit timer, ETU counter, with 3 configurable interrupt request output, the internal register read and write programming.
Platform: | Size: 5120 | Author: gab | Hits:
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