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[Other resourcersc_encode

Description: RSC编码的演示程序,用于turbo编码。-RSC coding Demonstration Program for turbo coding.
Platform: | Size: 945 | Author: dfsgsdfg | Hits:

[VHDL-FPGA-Veriloggongcehngsheji_477-2

Description: 使用该VHDL在仿真软件中实现RSC(递归系统卷积)码的编码以及解码硬件仿真-use of the VHDL simulation software in achieving RSC (recursive convolution system) code encoding and decoding hardware simulation
Platform: | Size: 6144 | Author: 李超 | Hits:

[Communicationturbodecode

Description: 第一个编码的程序调出来了,1/2的码率,用的是8×8行列交织器,rsc用的是 g0=[1 1 1],g1=[1 0 1]。算法是根据网格图来编写的。 信息输入是64bit的(0,1,0,1,0,1,0,1,0,0,、、、、、),最后结果是stream[128]=[00100110011000100101000001010101000001010101000001000101000101000101000101000101000001000100000001000100000001010100000101011011] 第二个译码程序用的是sova译码算法,迭代次数选的6,现在解码出来的信息是对的,和原输入编码器的信息位一致。 然后我有意把译码器输入stream序列打错几个bit都能正确译码。-err
Platform: | Size: 2048 | Author: 刘文 | Hits:

[MPIrsc_encode

Description: RSC编码的演示程序,用于turbo编码。-RSC coding Demonstration Program for turbo coding.
Platform: | Size: 1024 | Author: dfsgsdfg | Hits:

[Communication-MobileTURBO

Description: 用matlab实现的TURBO码编码。编码器由两个RSC卷积编码器构成-TURBO achieved with matlab coding. RSC encoder by the two convolutional encoder constitute
Platform: | Size: 1024 | Author: eric | Hits:

[VHDL-FPGA-VerilogRSC

Description: Turbo码编码器的两个分量编码器RSC,主要由四个移位寄存器和两个模2加法器组成-Turbo code encoder of the two component encoders RSC, mainly by the four shift register and the two-mode adder composed of 2
Platform: | Size: 1024 | Author: sunhao | Hits:

[Streaming Mpeg4H264AVCDecoderLibTestStatic

Description: Simulation of Turbo Encoding and Decoding" A randomly generated information bits are encoded with Turbo Encoder (which uses two RSC Encoders in parallel along with an interleaver) and added with AWG Noise then decoded with Turbo Decoder (Soft Output Viterbi Algorithm). We have understood/used TI TMS320C55x Processor and its assembly instruction set.
Platform: | Size: 291840 | Author: satya | Hits:

[Windows Developturbo

Description: map algorithm for turbo codes in matlab the simulation, using 1 / 2 code rate rsc and 2 - random interleaver
Platform: | Size: 16384 | Author: 刘阔 | Hits:

[3G developWIMAX_Turbo_Code

Description: 这是一套完整的支持wimax 16e协议CTC的编译码程序, 主程序在demo.c 译码器:tcdecoder.c 编码器:tcencoder.c-/* This program simulates the classical turbo encoding-decoding system on PC.*/ /* It uses parallel concatenated convolutional codes described in Figure 2.9 in Chapter 2.*/ /* Two component RSC (Recursive Systematic Convolutional) encoders are used. */ /* First encoder is terminated with tails bits. (Info+ tail) bits are scrambled and */ /* passed to the second encoder, while second encoder is left open without tail bits. */ /* Random information bits are modulated into+1/-1, and transmitted through an AWGN channel.*/ /* Interleavers are randomly generated for each frame.*/ /* Log-MAP algorithm without quantization or approximation is used.*/ /* By making use of ln(e^x+e^y) = max (x,y)+ ln(1+e^(-abs(x-y))), */ /* the Log-MAP is simplified with a look-up table for the correction term.*/ /* When the approximation ln(e^x+e^y) = max (x,y) is, we have MAX-Log-MAP.*/ /* To set the number of iterations, change the globle variable "DECITER". To set the fr
Platform: | Size: 26624 | Author: bennytang | Hits:

[matlabTurboencoder

Description: Turbo Encoder using RSC encoder with interleaver
Platform: | Size: 1024 | Author: selva | Hits:

[3G developturbo_sys_demo

Description: This script simulates the classical turbo encoding-decoding system. It simulates parallel concatenated convolutional codes. Two component rate 1/2 RSC (Recursive Systematic Convolutional) component encoders are assumed. First encoder is terminated with tails bits. (Info + tail) bits are scrambled and passed to the second encoder, while second encoder is left open without tail bits of itself. Random information bits are modulated into +1/-1, and transmitted through a AWGN channel. Interleavers are randomly generated for each frame. Log-MAP algorithm without quantization or approximation is used. By making use of ln(e^x+e^y) = max(x,y) + ln(1+e^(-abs(x-y))), the Log-MAP can be simplified with a look-up table for the correction function. If use approximation ln(e^x+e^y) = max(x,y), it becomes MAX-Log-MAP.- This script simulates the classical turbo encoding-decoding system. It simulates parallel concatenated convolutional codes. Two component rate 1/2 RSC (Recursive Systematic Convolutional) component encoders are assumed. First encoder is terminated with tails bits. (Info + tail) bits are scrambled and passed to the second encoder, while second encoder is left open without tail bits of itself. Random information bits are modulated into +1/-1, and transmitted through a AWGN channel. Interleavers are randomly generated for each frame. Log-MAP algorithm without quantization or approximation is used. By making use of ln(e^x+e^y) = max(x,y) + ln(1+e^(-abs(x-y))), the Log-MAP can be simplified with a look-up table for the correction function. If use approximation ln(e^x+e^y) = max(x,y), it becomes MAX-Log-MAP.
Platform: | Size: 2048 | Author: yk | Hits:

[3G developPCCCs-in-an-AWGN-channel-

Description: VS2010及IT++4.2下实现PCCC在AWGN信道上的仿真-This program simulates Parallel Concatenated Convolutional Codes (PCCCs) of coding rate 1/3 using a turbo decoder with two SISO RSC modules. Reference: S. Benedetto, D. Divsalar, G. Motorsi and F. Pollara, "A Soft-Input Soft-Output Maximum A posteriori (MAP) Module to Decode Parallel and Serial Concatenated Codes", TDA Progress Report, nov. 1996
Platform: | Size: 2048 | Author: raven | Hits:

[3G developSCCCs-in-an-AWGN-channel-

Description: VS2010及IT++4.2下实现SCCC在AWGN信道上的仿真-This program simulates Serially Concatenated Convolutional Codes (SCCCs) of coding rate 1/4 using a turbo decoder with a SISO NSC module and a SISO RSC module. Reference: S. Benedetto, D. Divsalar, G. Motorsi and F. Pollara, "A Soft-Input Soft-Output Maximum A posteriori (MAP) Module to Decode Parallel and Serial Concatenated Codes", TDA Progress Report, nov. 1996
Platform: | Size: 2048 | Author: raven | Hits:

[Communication-Mobileturbo_codes

Description: turbo encoder (two RSC encoder with random puncturing function)-turbo code
Platform: | Size: 9216 | Author: jinny | Hits:

[CommunicationRrscc_encoodeS

Description: RSC编码的演示程序源码,用于于turbo编码。 -Demonstration program of the RSC-coded source used for turbo codes.
Platform: | Size: 1024 | Author: | Hits:

[matlabturbo

Description: 主要是Turbo码的编码和译码,可以选择信噪比、 译码算法 还有图显示 可以直接使用 代码没有问题-This script simulates the classical turbo encoding-decoding system.It simulates parallel concatenated convolutional codes.Two component rate 1/2 RSC (Recursive Systematic Convolutional) component encoders are assumed.First encoder is terminated with tails bits. (Info+ tail) bits are scrambled and passed to the second encoder, while second encoder is left open without tail bits of itself.
Platform: | Size: 1797120 | Author: 韩东 | Hits:

[matlabTurbo

Description: simulate ber performance of example turbo code (rate-1/3, rsc = (1 5/7))
Platform: | Size: 3072 | Author: smuaini | Hits:

[Program docturbo-rsc

Description: turbo rsc With rs language matlab code encoding and decoding, together with veterbi algorithme decoding
Platform: | Size: 15360 | Author: reda | Hits:

[OthermyTurbo_test

Description: Turbo编码的FPGA实现,采用了(7,5)RSC编码和循环移位交织,帧长度128bit(The FPGA implementation of Turbo coding adopts (7, 5) RSC coding and cyclic shift interleaving, and the frame length is 128bit.)
Platform: | Size: 1808384 | Author: louisqw | Hits:

[Internet-NetworkTurbo_encode

Description: 实现了Turbo码编码的c语言模拟,采用了(7,5)RSC编码以及循环移位交织(The C language simulation of Turbo code is realized, with (7, 5) RSC coding and cyclic shift interleaving.)
Platform: | Size: 1024 | Author: louisqw | Hits:
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