Search - uart code in verilog

Search - uart code in verilog - List

[VHDL-FPGA-Verilog] S6_VGA_change DL : 0: verilog源代码，quartusII工程。程序实现VGA时序。控制VGA显示器输出图形。在quartusII中客直接运行，-Verilog source code, quartusII works. Procedures to achieve VGA timing. VGA graphics display control output. QuartusII in the direct run-off,
Update : 2025-02-17 Size : 2.45mb Publisher : 李晨
[VHDL-FPGA-Verilog] uart_51 DL : 0: 符合8051协议规范的UART的Verilog源代码.该压缩包是一个modelsim的工程.-8051 agreement in line with the norms of the Verilog source code UART. The Compression Pack is a ModelSim project.
Update : 2025-02-17 Size : 41kb Publisher : 王亮
[Com Port] uart DL : 0: this a Uart source code using Verilog.
Update : 2025-02-17 Size : 10kb Publisher : Daniel Zhang
[Com Port] uart(Verilog) DL : 0: RS232的verilog源代码,如果需要的可以-RS232 of Verilog source code, if necessary can be
Update : 2025-02-17 Size : 10kb Publisher : 陈强
[VHDL-FPGA-Verilog] fpga_uartrw DL : 0: FPGA的uart控制器的verilog源程序，在cyclone II EP2C8Q208上调试运行成功-FPGA s UART controller Verilog source code, in cyclone II EP2C8Q208 debugging run successfully
Update : 2025-02-17 Size : 54kb Publisher : 蒋斌斌
[VHDL-FPGA-Verilog] UART_for_FPGArar DL : 0: it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]-it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]
Update : 2025-02-17 Size : 5kb Publisher : yasir ateeq
[VHDL-FPGA-Verilog] UART DL : 0: 用FPGA开发的串口通信的程序，代码是用verilog编写的，希望对大家有用！-Serial communication with the FPGA development process, the code is written in verilog and hope for all of us!
Update : 2025-02-17 Size : 261kb Publisher : 郭富民
[Other] uart_rx DL : 0: Tcode is in VERILOG HDL (Hardware description language) code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA-Tcode is in VERILOG HDL (Hardware description language) code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA
Update : 2025-02-17 Size : 1kb Publisher : hassan
[VHDL-FPGA-Verilog] sim_uart DL : 0: uart 收发器 verilog 代码，实现自收发功能 sys clk = 25m, baud 9600 停止位1，无校验位；代码实现了串口自收发功能，及把从 PC 收到的内容都发送会 PC, 其他波特率，自行修改代码即可，在 alter 的FPGA 上调试通过； -verilog code uart transceiver to achieve self-transceiver function sys clk = 25m, baud 9600 1 stop bit, no parity code from the transceiver features a serial port, and the contents received from the PC will send the PC, another Potter rate, self-modifying code can, in the alter of the FPGA, debugging through
Update : 2025-02-17 Size : 2kb Publisher : 周西东
[VHDL-FPGA-Verilog] FPGA_UART DL : 0: 用Verilog语言实现的FPGA UART独立收发模块思路简单，代码简洁。在Lattice LFE3EA VERSA开发板上验证通过,编译器Lattice Diamond. 功能：串口收到数据后立即回传，此后每一秒串口数据+1再发送。-Using Verilog language independent of FPGA UART transceiver idea is simple, concise code. Development board in Lattice LFE3EA VERSA verified by the compiler Lattice Diamond. Features: Serial data is received immediately after the return, then every second serial port and then send the data+ 1.
Update : 2025-02-17 Size : 3kb Publisher : 朱强光
[VHDL-FPGA-Verilog] UART_send DL : 0: uart的verilog代码，在赛灵思的spartan 3E上经过验证，电路有一定的质量。-The verilog uart code, in the spirit of the best Spartan 3 E after verification, circuit has certain quality.
Update : 2025-02-17 Size : 1.62mb Publisher : skjin
[VHDL-FPGA-Verilog] UART_acpt DL : 0: The verilog uart code, in the spirit uart的verilog代码，在赛灵思的spartan 3E上经过验证，电路有一定的质量。-The verilog uart code, in the spirit of the best Spartan 3 E after verification, circuit has certain quality.
Update : 2025-02-17 Size : 399kb Publisher : skjin
[VHDL-FPGA-Verilog] Uart DL : 0: UART source code in verilog
Update : 2025-02-17 Size : 1kb Publisher : Sweetu
[Other] 1.UART DL : 0: 该代码主要实现UART的串行通信，针对的是RS232芯片，同时包含了verilog和VHDL编写的程序-The code UART serial communication, RS232 chip, also contains a program written in verilog and VHDL
Update : 2025-02-17 Size : 1.43mb Publisher : mingbo
[Software Engineering] UART DL : 0: 基于ISE 用verilog编写的uart串口通信源码-Based on the ISE written in verilog uart serial communication source code
Update : 2025-02-17 Size : 1kb Publisher : 祁伟
[VHDL-FPGA-Verilog] UART-Verilog-source DL : 0: Verilog编写UART串口例程，实现FPGA与上位机串口通信，利用ASCII码进行大小写转换，在Xilinx Virtex-5开发板测试通过-UART serial routines written in Verilog, FPGA serial communication with the host computer using the ASCII code case conversion, in the Xilinx Virtex-5 development board test
Update : 2025-02-17 Size : 3kb Publisher : charley
[VHDL-FPGA-Verilog] UART DL : 0: Verilog HDL编写的串口程序实例，很详细好用的参考代码。针对Xilinx FPGA开发板，在Xilinx ISE编译调试成功，串口开发的经典例程。-Verilog HDL serial program written examples, very good reference code in detail. In view of the Xilinx FPGA development board, in Xilinx ISE compiler debugging success, a serial port development of classic routines.
Update : 2025-02-17 Size : 214kb Publisher : 韩建平
[VHDL-FPGA-Verilog] rs232 DL : 0: verily 串口rs232代码，可参数化波特率-uart code in verilog
Update : 2025-02-17 Size : 2kb Publisher : wushaowei
[VHDL-FPGA-Verilog] LIFO_Spartan3 DL : 0: The code for a LIFO in verilog
Update : 2025-02-17 Size : 494kb Publisher : sadii
[VHDL-FPGA-Verilog] uart DL : 0: FPGA Verilog设计UART通讯程序(UART communication code with Verilog in FPGA)
Update : 2025-02-17 Size : 115kb Publisher : gq_zhou

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