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[VHDL-FPGA-Verilog] uart from opencores

Description: 用VHDL实现串口 可以实现与pc机的通信 收发 中断都可以 效果比较好-VHDL implement serial port, it can communicate with pc, it can accept and send message, and it can be interrupted.
Platform: | Size: 9216 | Author: 熊明 | Hits:

[VHDL-FPGA-Verilog] vhdl0716

Description: ISE7.1，采用VIRTEX-II芯片。实现adc数据采样，平均，通道选择，采样时钟选择，数据格式调整，内含fifo,uart等模块。-ISE7.1, using VIRTEX-II chip. Adc realize data sampling, on average, channel selection, the sampling clock select, adjust data formats, including fifo, uart modules.
Platform: | Size: 8431616 | Author: 杨奋燕 | Hits:

[Other Embeded program] uart

Description: ARN7核s3c44b0串口程序源码,包括FIFO,非FIFO多模式的接收发送.-S3C44B0 serial ARN7 nuclear program source code, including FIFO, non-FIFO multi-mode receiver sent.
Platform: | Size: 4096 | Author: 雪莱 | Hits:

[VHDL-FPGA-Verilog] tx

Description: 自己编写的串口UART发送的Verilog模块。与FIFO连接，可以实现自动连续发送。-I have written serial UART to send the Verilog module. Connect with the FIFO, you can realize automatic continuous send.
Platform: | Size: 7168 | Author: YongZhiLi | Hits:

[ARM-PowerPC-ColdFire-MIPS] uart

Description: mega128串口通讯源码API函数，中断方式-Serial Communication mega128 source API function, interruption mode
Platform: | Size: 2048 | Author: liuyingjie | Hits:

[Communication-Mobile] uart

Description: 这个是UART的控制器，已经跑通过，分4个模块，波特率生成、发送、接收和fifo,可供初学者参考-This is the UART controller, has been run through, sub-4 module, baud rate generating, sending, receiving and fifo, for beginners reference
Platform: | Size: 3072 | Author: duan | Hits:

[VHDL-FPGA-Verilog] uart_regs

Description: 可以直接下载到芯片用的带有FIFO的完全UART程序，vhdl语言编写。-Can be directly downloaded to the chip used in the complete UART with FIFO procedures, vhdl language.
Platform: | Size: 388096 | Author: liujingxing | Hits:

[Embeded-SCM Develop] ARM_UART

Description: 基于arm—LPC2103的串口通讯程序，用上了uart 的FIFO实现。-Arm-LPC2103-based serial communication program, with the use of the UART
Platform: | Size: 52224 | Author: chengjiang | Hits:

[VHDL-FPGA-Verilog] UART

Description: 使用FPGA的FIFO，状态机，乒乓操作等实现了异步UART。-The use of FPGA-FIFO, state machine, ping-pong operation to achieve the asynchronous UART.
Platform: | Size: 1106944 | Author: xiao cao | Hits:

[Com Port] Uart(FIFOSend.TimeoutReceive)

Description: AVR mega16/mega32的UART FIFO发送.超时接收,广泛应用于工业控制.这是原创作品.-AVR mega16/mega32 send the UART FIFO. Overtime receiver is widely used in industrial control. This is the original works.
Platform: | Size: 24576 | Author: 明君 | Hits:

[Embeded-SCM Develop] uart_fifo

Description: avr单片机串口先进先出实例程序，这是个人在实际项目中应用的一个例子，还有是定时器的使用方法-Examples of single-chip FIFO serial avr procedures, which are individual projects in the actual application of an example are also the use of timer
Platform: | Size: 16384 | Author: 张子凤 | Hits:

[Other Embeded program] int_uart8051

Description: UART realization for at89c5131 with FIFO and interrupts.
Platform: | Size: 1024 | Author: melg | Hits:

[OS Develop] UART

Description: A badic controller for the UART. It incorporates a -- transmit and receive FIFO (from Max+Plus II s MegaWizard -- plug-in manager). Note that no checking is done to see -- whether the FIFOs are overflowing or not. This strictly -- handles the transmitting and receiving of the data.-A badic controller for the UART. It incorporates a -- transmit and receive FIFO (from Max+Plus II s MegaWizard -- plug-in manager). Note that no checking is done to see -- whether the FIFOs are overflowing or not. This strictly -- handles the transmitting and receiving of the data.
Platform: | Size: 2048 | Author: Viral | Hits:

[SCM] FIFO-UART

Description: 基于ARM7-LM3S1138的FIFO方式的UART数据传输代码-ARM7-LM3S1138 based on the FIFO mode of UART data transmission code
Platform: | Size: 44032 | Author: Mr Zhang | Hits:

[Other] uart

Description: 此文档为C51单片机串口通讯学习程序（中断+FIFO)-This document is for the C51 microcontroller serial communication learning process (interrupted+ FIFO)
Platform: | Size: 6144 | Author: | Hits:

[ARM-PowerPC-ColdFire-MIPS] UART-FIFO

Description: easy arm1138 UART-FIFO 收发程序-easy arm1138 UART-FIFO receive program
Platform: | Size: 104448 | Author: yangsiyuan | Hits:

[VHDL-FPGA-Verilog] UART

Description: 基于FPGA的UART设计，包含接收模块，发送模块，FIFO模块-UART FPGA-based design, including the receiver module, sending module, FIFO module
Platform: | Size: 733184 | Author: 钱远盼 | Hits:

[SCM] UART-fifo-memcpy

Description: S3C2440上的UART读取实现使用fifo缓冲区,并且用memcpy实现，加快运行速度-S3C2440 UART fifo memcpy
Platform: | Size: 3072 | Author: 黄建华 | Hits:

[VHDL-FPGA-Verilog] uart

Description: 带有fifo的功能模块，具有发送模块和接收功能模块(The function module with FIFO has transmitting module and receiving function module)
Platform: | Size: 145408 | Author: 陈陈陈啊 | Hits:

[SCM] fifo

Description: 一个简单的FIFO实现，基于STM32的UART+DMA方式。(A simple FIFO implementation, based on the STM32 UART+DMA approach.)
Platform: | Size: 1024 | Author: 与众漫步 | Hits:
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