Search - uart ip core

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[Driver Develop] ata_ip DL : 0: ATA接口的IP核,经过量产的验证,已经在quartus5.1下编译通过了.-ATA interface IP core, after volume production test in quartus5.1 compiler passed.
Update : 2025-02-17 Size : 499kb Publisher : 李想
[VHDL-FPGA-Verilog] uart_core DL : 0: UART RS232 IPCORE for sopc builder -RS232 UART IPCORE for sopc builder
Update : 2025-02-17 Size : 109kb Publisher : 张建
[VHDL-FPGA-Verilog] fftinterface DL : 0: 电赛一等奖作品：音频信号分析仪的FPGA源码，VHDL编写，Quartus7.1综合，ModelSim6.2g se仿真，应用了opencores.org上的开源FFT IP核，加入了8051总线接口和ram-Xinhua Cup first prize works: audio signal analyzer FPGA source, VHDL prepared, Quartus7.1 integrated, ModelSim6.2g se simulation, application of open source opencores.org on FFT IP core, joined the 8051 bus interface and ram
Update : 2025-02-17 Size : 4.71mb Publisher : 李星
[VHDL-FPGA-Verilog] uart16550.tar DL : 0: uart16550 ip core 通用异步收发器vhdl源代码-uart16550 ip core UART VHDL source code
Update : 2025-02-17 Size : 241kb Publisher : 姓名
[VHDL-FPGA-Verilog] uartvhdl DL : 0: VHDL语言实现的UART IP核，比较实用-VHDL language to achieve the UART IP core, more practical
Update : 2025-02-17 Size : 403kb Publisher : 蔡飞
[VHDL-FPGA-Verilog] uart8 DL : 0: 使用Libero提供的异步通信IP核实现UART通信，并附带仿真程序。UART设置为1位开始位，8位数据位，1位停止位，无校验。且UART发送自带2级FIFO缓冲，占用FPGA面积很小。-Libero provided the use of asynchronous communication IP core implementation UART communications, and incidental simulation program. UART is set to 1 to start bit, 8 data bits, 1 stop bit, no parity. UART and send its own two FIFO buffer occupancy is very small FPGA.
Update : 2025-02-17 Size : 856kb Publisher : 张键
[VHDL-FPGA-Verilog] uart_serial DL : 0: UART IP core in VHDL
Update : 2025-02-17 Size : 10kb Publisher : zhanglh
[VHDL-FPGA-Verilog] UARTipcore DL : 0: 这是一个关于UART的IP核，用VHDL写的。经过本人的鉴证，非常实用并且写的非常好。-This is one of the IP core on the UART, using VHDL written. After my verification, very practical and very well written.
Update : 2025-02-17 Size : 22kb Publisher : 11
[VHDL-FPGA-Verilog] uart16550_latest[1].tar DL : 0: 开源UART IP核16550，该IP核兼容16550 UART，具有Modem功能，完全可编程的串行接口具有可设置的字符长度、奇偶校验、停止位以及波特率生成器。-Open-source UART IP core 16550, the IP core is compatible with 16550 UART, with Modem function, fully programmable serial interface can be set up with a character length, parity, stop bits and baud rate generator.
Update : 2025-02-17 Size : 1.49mb Publisher : lisa1027
[VHDL-FPGA-Verilog] fifoed_avalon_uart9.1_applicaton DL : 0: 用于Altera Avalon总线的、具有FIFO缓冲的Uart数据串口IP核以及应用于Nios2的、真正可运行的、容易移植的C代码。-Fifoed avalon uart IP core and C code for the IP core.
Update : 2025-02-17 Size : 201kb Publisher : xmar
[Software Engineering] FPGA_RS232 DL : 0: 为增加系统稳定性，减小电路板面积，提出一种基于FPGA的异步串行口IP核设计。该设计使用VHDL硬件描述语言时接收和发送模块在Xilinx ISE环境下设计与仿真。最后在FPGA上嵌入UART IP核实现电路的异步串行通信功能。该IP核具有模块化、兼容性和可配置性，可根据需要实现功能的升级、扩充和裁减。-In order to increase system stability, reduce board space, presents a FPGA-based asynchronous serial port IP-core design. The design using the VHDL hardware description language to receive and transmit modules in Xilinx ISE design and simulation environment. Finally, embedded UART IP core on the FPGA circuit implementation of the asynchronous serial communications. The IP core has a modular, compatibility and configurability, can achieve the functionality needed upgrade, expansion and reduction.
Update : 2025-02-17 Size : 210kb Publisher : jalon
[VHDL-FPGA-Verilog] UART_IP_core_for_wishbone DL : 0: 基于wishbone总线的UART IP core-UART IP core based on Wishbone, generated in Verilog HDL.
Update : 2025-02-17 Size : 39kb Publisher : 张阳
[VHDL-FPGA-Verilog] RS232_NIOS_Verilog DL : 0: 5个文件，包含了RS232的nios实现和Verilog实现方式。其中,RS232的nios核实现只需要按照文件描述可以轻松实现^_^，个人比较推荐！RS232的Verilog实现需要编程，例程方便使用。RS232正在进一步学习中，有兴趣的可以探讨。-the realizition of rs232 interface by niosii uart ip core of Altera.it seems a most conveniet way.
Update : 2025-02-17 Size : 669kb Publisher : summerooooo
[VHDL-FPGA-Verilog] UART DL : 0: 用硬件描述语言实现的uart的IPcore，有详细的注释和测试文件-Hardware description language of the H.264 encoder, detailed notes and test files
Update : 2025-02-17 Size : 22kb Publisher : wt
[VHDL-FPGA-Verilog] uart DL : 0: uart IP CORE Verilog quartus-uart IP CORE Verilog quartusii
Update : 2025-02-17 Size : 36kb Publisher : thegreeneyes
[SCM] sd_card DL : 0: 面向altera公司的大学计划sd-card ip核，检测sd卡是否插入卡槽中。-Altera company s University Program for sd-card ip core, testing sd card is inserted into the card slot
Update : 2025-02-17 Size : 1.57mb Publisher : 陈小林
[VHDL-FPGA-Verilog] FIFOED_UART DL : 0: CAL_UART核verilog源码，带FIFO，FIFO深度可设置。-fifoed uart ip core. cal_uart.
Update : 2025-02-17 Size : 6kb Publisher : 杨胜尧
[Com Port] uart-IP-Core DL : 0: 串口的FPGA VHDL的IP核可以直接调用使用-Serial FPGA VHDL IP core can be called directly use
Update : 2025-02-17 Size : 315kb Publisher : 吴星
[VHDL-FPGA-Verilog] UART DL : 0: 1.UART是一个UART的IP核，在其它的程序中可以直接的调用的,波特率是9600.-Is 1.UART a UART IP core can directly call the other program, the baud rate is 9600.
Update : 2025-02-17 Size : 1.94mb Publisher : 金华
[VHDL-FPGA-Verilog] UART-IP-based-on-queue DL : 0: 基于队列传输的UART的IP核程序，已调试可直接使用。-Queue-based transmission of UART IP core procedures have been debugging can be used directly.
Update : 2025-02-17 Size : 10kb Publisher : 瞿盛

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