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[VHDL-FPGA-Verilog] scorce

Description: FPGA驱动1602LCD程序，在实验板上实验成功，和大家分享！^_^-FPGA-driven 1602LCD procedures, the success of the experiment on-board experiments, and the U.S. to share! ^ _ ^
Platform: | Size: 2048 | Author: whq | Hits:

[VHDL-FPGA-Verilog] kp_uart

Description: This UART and LCD interface C code Tested on Sparton 3 xilinx FPGA.-This is UART and LCD interface C code Tested on Sparton 3 xilinx FPGA.
Platform: | Size: 3072 | Author: bhagwan | Hits:

[Embeded-SCM Develop] UART

Description: A simple preoteus based design to display the characters typed int the keyboard into LCD using UART of 8051.Plz make sure that TTL to RS232 is inserted in between the microcontroller and virtual terminal which is not shown in the design.
Platform: | Size: 45056 | Author: sandeep | Hits:

[Software Engineering] VHDL-PROJECT030609

Description: parallel communication UART without LCD
Platform: | Size: 543744 | Author: Daniel R. | Hits:

[VHDL-FPGA-Verilog] topone

Description: 基于火龙刀开发板的FPGA和PC的UART串口通信的VHDL实现，支持LCD实现分页显示和LED 数码管显示。-FPGA and PC UART communication module implemented by VHDL, running on Dragon platform, with support of LCD and LED display.
Platform: | Size: 19456 | Author: bingo | Hits:

[Com Port] UART_VHDLCodes

Description: 基于VHDL的异步串口收发器，在FPGA上设计Uart接收模块实现从pc接收串口数据； 在FPGA上设计Uart发送模块，把从pc接收的数据的16进制值加1再发送给PC； 设计单片机和FPGA接口模块，把接收到的数据送给单片机，并显示在LCD上 -VHDL-based asynchronous serial transceivers Uart receive module in the FPGA design from pc to receive serial data design the Uart send module on FPGA, the hexadecimal value of the data received from the pc plus 1 and then sent to a PC design microcontroller and FPGA interface module, the received data sent to the MCU, and displayed on the LCD
Platform: | Size: 427008 | Author: katheqiu | Hits:

[VHDL-FPGA-Verilog] uart_lcd

Description: 基于FPGA的UART通信，并用LCD(1602)显示通讯状态和通讯的数据。通过在ALTERA公司生产的DE2-115开发板上运行，证明此程序稳定可靠。时钟为50MHz，语言为VHDL,状态机。-FPGA-based UART communication, and LCD (1602) show the communication status and data communications. DE2-115 development board by ALTERA Company production run, prove that the program is stable and reliable. The clock is 50MHz, language VHDL, state machines.
Platform: | Size: 6435840 | Author: jiazhaorong | Hits:

[DSP program] code

Description: vhdl code which includes various codes of clock divider uart lcd etc
Platform: | Size: 2028544 | Author: devi | Hits:

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