Description: 这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序,用verilog实现,ise7.1,不知道这里可不可以上传硬件的程序~-pci-wishbone nuclear and nuclear Serial 16,450 in the TP xilinx They achieved a serial program, verilog realization ise7.1. Can here do not know the procedures upload hardware ~ Platform: |
Size: 8427520 |
Author:heartbeat |
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Description: xilinx官网提供的VHDL,UART串行通信模块,肯定好用,官方提供-xilinx official website provides VHDL, UART, FPGA communication module is certainly easy to use, official Platform: |
Size: 10240 |
Author:雪尘 |
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Description: Verilog编写UART串口例程,实现FPGA与上位机串口通信,利用ASCII码进行大小写转换,在Xilinx Virtex-5开发板测试通过-UART serial routines written in Verilog, FPGA serial communication with the host computer using the ASCII code case conversion, in the Xilinx Virtex-5 development board test Platform: |
Size: 3072 |
Author:charley |
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Description: Verilog HDL编写的串口程序实例,很详细好用的参考代码。针对Xilinx FPGA开发板,在Xilinx ISE编译调试成功,串口开发的经典例程。-Verilog HDL serial program written examples, very good reference code in detail. In view of the Xilinx FPGA development board, in Xilinx ISE compiler debugging success, a serial port development of classic routines. Platform: |
Size: 219136 |
Author:韩建平 |
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Description: Verilog 实现的 UART串口读写控制核 参数化校验、时钟设置,完整工程(xilinx),包括文档、源码等。供学习参考,希望大家上传自己代码,共同提高,打倒小日本。-Verilog implementation of the UART serial port to read and write control nuclear parametric check, clock setting, complete project (Xilinx), including documentation, source code and so on. For learning reference, hope you upload your own code, improve together, little japanese. Platform: |
Size: 423936 |
Author:FEIFEI |
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Description: 利用xilinx 公司的ise软件基于verilog HDL实现UART控制程序-based on the xilinx ise and use verilog HDL language to achieve the purposes that control the uart. Platform: |
Size: 65536 |
Author:尚文东 |
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Description: Verilog TUTORIAL for beginners. We had earlier published a Verilog tutorial that made use of the Xilinx ISE Simulator. Platform: |
Size: 57344 |
Author:kimluan |
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