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[VHDL-FPGA-Verilog] USB 1.1 IP-CORE和设计范例 VHDL源代码 DL : 0: USB 1.1 IP-CORE和设计范例 VHDL源代码-Sample program for USB1.1 IP core design, VHDL source code
Update : 2025-02-17 Size : 416kb Publisher : ken
[VHDL-FPGA-Verilog] usb1.1_Verilog DL : 1: usb1.1的设备控制器IP核，是用verilog硬件描述语言写的-USB1.1 IP core for device control, written with hardware describing language of Verilog.
Update : 2025-02-17 Size : 128kb Publisher : 李恒
[USB develop] usb_doc DL : 0: USB IP core.very good
Update : 2025-02-17 Size : 139kb Publisher : 张卫
[VHDL-FPGA-Verilog] USB IPcore（带说明） DL : 0: USB IPcoreIP核，包含文档（带说明）-USB IPcoreIP nuclear contains documents (with the note)
Update : 2025-02-17 Size : 399kb Publisher : 陈友荣
[VHDL-FPGA-Verilog] USB 2.0 IP Core DL : 0: USB20的IP CORE,可以直接用在SOPC下，自动完成全部的枚举，只需修改枚举参数即可！-USB20 IP CORE, can be directly used in SOPC, automatically complete the enumeration. only a modification of enumerated parameters can be!
Update : 2025-02-17 Size : 177kb Publisher : 林风
[VHDL-FPGA-Verilog] USB2.0IP_core_Verilog DL : 0: 完整的用VERILOG语言开发的USB2.0 IP核源代码，包括文档、仿真文件-complete with verilog language development USB2.0 IP source code, including documentation, Simulation documents
Update : 2025-02-17 Size : 202kb Publisher : 张清平
[VHDL-FPGA-Verilog] USB_2-0_Host_IP_Core DL : 0: this come from alter ,you can look and find it on line about USB
Update : 2025-02-17 Size : 87kb Publisher : fff
[Other Embeded program] usb11_test DL : 0: 该范例使用FreeDev_usb11 ip core支持开发板成为USB HOST的设备（常见的是PC机）。
Update : 2025-02-17 Size : 58kb Publisher : HuFengzhang
[Other Embeded program] ip DL : 0: usart的verilog代码.rar 包括很多的FPGA ip 源码，可以直接应用 uart_vhdl.zip sl811usb包含源程序.rar mc8051_design.zip mcpu_1[1].05.zip minicpu.zip mmc_lark_original.zip -USART the Verilog code. rar, including many of the FPGA ip source, can be applied directly uart_vhdl.zipsl811usb contains the source code. rarmc8051_design.zipmcpu_1 [1] .05. zipminicpu.zipmmc_lark_original.zip
Update : 2025-02-17 Size : 5.14mb Publisher : 钟阳
[Other] free_IP_1 DL : 0: 来自于OpenCores组织的开放IP核，非常专业，大牛编写。-OpenCores organizations from open IP core, very professional, big cattle preparation.
Update : 2025-02-17 Size : 2.52mb Publisher : wangyunshann
[USB develop] usb_phy DL : 0: usb接口协议。It was tested with a USB 1.1 core I have written on a XESS XCV800 board with a a Philips PDIUSBP11A transceiver. -usb interface protocol. It was tested with a USB 1.1 core I have written ona XESS XCV800 board with aa Philips PDIUSBP11A transceiver.
Update : 2025-02-17 Size : 11kb Publisher : 颜新卉
[USB develop] usb20_ipcore_usb_funct DL : 0: usb的芯片ip core. 用HDL描述，适合asic/fpga人员参考或使用。USB ip core for ASIC/FPGA designers.-usb chips ip core. with HDL description suitable for asic/fpga staff reference or use. USB ip core for ASIC/FPGA designers.
Update : 2025-02-17 Size : 204kb Publisher : road
[VHDL-FPGA-Verilog] USB DL : 0: 用VHDL实现的USB IP核，大家可以参考下-Use VHDL to achieve USB IP core, we can refer to the following
Update : 2025-02-17 Size : 1.09mb Publisher : 蔡飞
[USB develop] usb DL : 0: USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-bit Wishbone slave bus interface. – FIFO depth configurable via paramters.-USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-bit Wishbone slave bus interface. – FIFO depth configurable via paramters.
Update : 2025-02-17 Size : 6kb Publisher : polito
[VHDL-FPGA-Verilog] usb DL : 0: USB完整代码包括vhdl和verilog两种-usb ip core
Update : 2025-02-17 Size : 254kb Publisher : 王强
[USB develop] TSMC_DSD-USB-IP DL : 0: TSMC USB IP Spec for 0.18um proce-TSMC USB IP Spec for 0.18um process
Update : 2025-02-17 Size : 215kb Publisher : lht
[VHDL-FPGA-Verilog] verilog-usb--protel-design DL : 1: 基于FPGA的usb2.0 ip核设计，所用的语言是verilog-FPGA-based usb2.0 ip core design, the language used is the verilog
Update : 2025-02-17 Size : 52kb Publisher : 唐明桂
[USB develop] USB-1.1-IP-CORE-VHDL DL : 0: USB1.1标准接口的IP核的实现和其设计实现的源码范例VHDL-USB1.1 standard interface IP core implementations and examples of their design and implementation of the VHDL source code
Update : 2025-02-17 Size : 416kb Publisher : sxhfjgl010
[Documents] pg137-axi-usb2-device(xilinx USB ip core) DL : 0: xilinx USB ip 核使用说明文档，接口完全和usb3320接口一致(Xilinx USB IP core usage instructions document, the interface is completely consistent with the usb3320 interface)
Update : 2025-02-17 Size : 700kb Publisher : 黄国锋
[USB develop] usbip-win-master DL : 0: USB/IP emulator for windows 10 x64
Update : 2025-02-17 Size : 381kb Publisher : Illay999Devel

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