Search - usb ip

[VHDL-FPGA-Verilog] USB 1.1 IP-CORE和设计范例 VHDL源代码

Description: USB 1.1 IP-CORE和设计范例 VHDL源代码-Sample program for USB1.1 IP core design, VHDL source code
Platform: | Size: 425984 | Author: ken | Hits:

[VHDL-FPGA-Verilog] usb1.1_Verilog

Description: usb1.1的设备控制器IP核，是用verilog硬件描述语言写的-USB1.1 IP core for device control, written with hardware describing language of Verilog.
Platform: | Size: 131072 | Author: 李恒 | Hits:

[USB develop] usb_doc

Description: USB IP core.very good
Platform: | Size: 142336 | Author: 张卫 | Hits:

[VHDL-FPGA-Verilog] USB IPcore（带说明）

Description: USB IPcoreIP核，包含文档（带说明）-USB IPcoreIP nuclear contains documents (with the note)
Platform: | Size: 408576 | Author: 陈友荣 | Hits:

[VHDL-FPGA-Verilog] USB 2.0 IP Core

Description: USB20的IP CORE,可以直接用在SOPC下，自动完成全部的枚举，只需修改枚举参数即可！-USB20 IP CORE, can be directly used in SOPC, automatically complete the enumeration. only a modification of enumerated parameters can be!
Platform: | Size: 181248 | Author: 林风 | Hits:

[VHDL-FPGA-Verilog] USB2.0IP_core_Verilog

Description: 完整的用VERILOG语言开发的USB2.0 IP核源代码，包括文档、仿真文件-complete with verilog language development USB2.0 IP source code, including documentation, Simulation documents
Platform: | Size: 206848 | Author: 张清平 | Hits:

[VHDL-FPGA-Verilog] USB_2-0_Host_IP_Core

Description: this come from alter ,you can look and find it on line about USB
Platform: | Size: 89088 | Author: fff | Hits:

[Other Embeded program] usb11_test

Description: 该范例使用FreeDev_usb11 ip core支持开发板成为USB HOST的设备（常见的是PC机）。
Platform: | Size: 59392 | Author: HuFengzhang | Hits:

[Other Embeded program] ip

Description: usart的verilog代码.rar 包括很多的FPGA ip 源码，可以直接应用 uart_vhdl.zip sl811usb包含源程序.rar mc8051_design.zip mcpu_1[1].05.zip minicpu.zip mmc_lark_original.zip -USART the Verilog code. rar, including many of the FPGA ip source, can be applied directly uart_vhdl.zipsl811usb contains the source code. rarmc8051_design.zipmcpu_1 [1] .05. zipminicpu.zipmmc_lark_original.zip
Platform: | Size: 5391360 | Author: 钟阳 | Hits:

[Other] free_IP_1

Description: 来自于OpenCores组织的开放IP核，非常专业，大牛编写。-OpenCores organizations from open IP core, very professional, big cattle preparation.
Platform: | Size: 2644992 | Author: wangyunshann | Hits:

[USB develop] usb_phy

Description: usb接口协议。It was tested with a USB 1.1 core I have written on a XESS XCV800 board with a a Philips PDIUSBP11A transceiver. -usb interface protocol. It was tested with a USB 1.1 core I have written ona XESS XCV800 board with aa Philips PDIUSBP11A transceiver.
Platform: | Size: 11264 | Author: 颜新卉 | Hits:

[USB develop] usb20_ipcore_usb_funct

Description: usb的芯片ip core. 用HDL描述，适合asic/fpga人员参考或使用。USB ip core for ASIC/FPGA designers.-usb chips ip core. with HDL description suitable for asic/fpga staff reference or use. USB ip core for ASIC/FPGA designers.
Platform: | Size: 208896 | Author: road | Hits:

[VHDL-FPGA-Verilog] USB

Description: 用VHDL实现的USB IP核，大家可以参考下-Use VHDL to achieve USB IP core, we can refer to the following
Platform: | Size: 1146880 | Author: 蔡飞 | Hits:

[USB develop] usb

Description: USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-bit Wishbone slave bus interface. – FIFO depth configurable via paramters.-USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-bit Wishbone slave bus interface. – FIFO depth configurable via paramters.
Platform: | Size: 6144 | Author: polito | Hits:

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list

[VHDL-FPGA-Verilog] USB 1.1 IP-CORE和设计范例 VHDL源代码

[VHDL-FPGA-Verilog] usb1.1_Verilog

[USB develop] usb_doc

[VHDL-FPGA-Verilog] USB IPcore（带说明）

[VHDL-FPGA-Verilog] USB 2.0 IP Core

[VHDL-FPGA-Verilog] USB2.0IP_core_Verilog

[VHDL-FPGA-Verilog] USB_2-0_Host_IP_Core

[Other Embeded program] usb11_test

[Other Embeded program] ip

[Other] free_IP_1

[USB develop] usb_phy

[USB develop] usb20_ipcore_usb_funct

[VHDL-FPGA-Verilog] USB

[USB develop] usb

[VHDL-FPGA-Verilog] usb

[USB develop] TSMC_DSD-USB-IP

[VHDL-FPGA-Verilog] verilog-usb--protel-design

[USB develop] USB-1.1-IP-CORE-VHDL

[Documents] pg137-axi-usb2-device(xilinx USB ip core)

[USB develop] usbip-win-master

CodeBus www.codebus.net