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[Other resource] usb2[1].0

Description: usb源码下载，是基于windows开发平台的，通过FPGA加以仿真验证。可以进行数据的传输-usb download the source code is based on the Windows platform, to be adopted FPGA simulation. Can be the transmission of data
Platform: | Size: 197895 | Author: 郑千洪 | Hits:

[Other resource] usb_2

Description: usb2的FPGA实现，verilog语句-usb2 FPGA, verilog statement
Platform: | Size: 196910 | Author: lious | Hits:

[Communication] USB2.0

Description: usb+fpga开发板电路图，PDF格式，可以用来学习USB2.0相关程序开发
Platform: | Size: 106195 | Author: 江汉 | Hits:

[Other resource] USB2.0+FPGA+DSP

Description: usb2.0 + fpga + dsp 开发板的原理图，希望对大家有用
Platform: | Size: 126108 | Author: 李明金 | Hits:

[USB develop] FPGA实现USB2　　

Description: FPGA实现USB2　原理-FPGA USB2 Principle
Platform: | Size: 114211 | Author: 陈平 | Hits:

[Other] 基于FPGA的USB2

Description:

介绍了一种用VHDL设计USB2.0功能控制器的方法，详术了其原理和设计思想，并在FPGA上予以实现。


Platform: | Size: 156672 | Author: nanhaijiaolong | Hits:

[USB develop] FPGA实现USB2　　

Description: FPGA实现USB2　原理-FPGA USB2 Principle
Platform: | Size: 113664 | Author: 陈平 | Hits:

[VHDL-FPGA-Verilog] usb2[1].0

Description: usb源码下载，是基于windows开发平台的，通过FPGA加以仿真验证。可以进行数据的传输-usb download the source code is based on the Windows platform, to be adopted FPGA simulation. Can be the transmission of data
Platform: | Size: 197632 | Author: | Hits:

[VHDL-FPGA-Verilog] usb_2

Description: usb2的FPGA实现，verilog语句-usb2 FPGA, verilog statement
Platform: | Size: 196608 | Author: lious | Hits:

[Driver Develop] ZSLoader

Description: usb2.0－68013 固件程序自动更新，驱动原码～～做usb的哥们推荐-usb2.0- 68013 firmware update automatically, Drivers original code ~ ~ do usb look at the recommendation of the Miners
Platform: | Size: 136192 | Author: 林铖涵 | Hits:

[VHDL-FPGA-Verilog] usb_funct[1].tar

Description: usb2.0的IP核，可在QuartusII或MaxPlusII环境下实现编译和生成ip核-usb2.0 IP nuclear, QuartusII or the environment under MaxPlusII compile and generate nuclear ip
Platform: | Size: 181248 | Author: 刘洋 | Hits:

[Embeded-SCM Develop] USB_test

Description: NIOS II 与USB接口的程序，用于周立功FPGA的开发板，自己的开发板只需修改引脚即可-NIOS II with the USB interface procedures for weeks Ligong FPGA development board, its own development board can only modify pin
Platform: | Size: 60416 | Author: weikang | Hits:

[Program doc] USB2.0

Description: usb+fpga开发板电路图，PDF格式，可以用来学习USB2.0相关程序开发-usb+ fpga development board schematics, PDF format, can be used to study the development of related procedures USB2.0
Platform: | Size: 105472 | Author: 江汉 | Hits:

[DSP program] USB2.0+FPGA+DSP

Description: usb2.0 + fpga + dsp 开发板的原理图，希望对大家有用-usb2.0+ fpga+ dsp development board schematic diagram, in the hope that useful to everybody
Platform: | Size: 125952 | Author: 李明金 | Hits:

[USB develop] USB2.0FPGA_EXAMPLES

Description: FPGA与USB通信的测试代码，包括FPGA中的程序（Verilog编写）和PC机上的主控程序以及USB固件程序。-FPGA and the USB communication test code, including the FPGA in the procedure [Verilog prepared] and PC-control procedures, as well as the USB firmware.
Platform: | Size: 5515264 | Author: 李诚铭 | Hits:

[USB develop] USB2.0FPGAEXAMPLES

Description: 用于USB20芯片CY7C68013和FPGA之间的通信-comunication between USB and FPGA
Platform: | Size: 2853888 | Author: 熊小姐 | Hits:

[VHDL-FPGA-Verilog] USB2.0

Description: usb2.0 fpga程序 用vhdl语言编写 quartus环境实现 -usb2.0 fpga using vhdl language program quartus environment to achieve
Platform: | Size: 3567616 | Author: PETER | Hits:

[Software Engineering] AReconfigurableFIRFilterSystemBasedonFPGA

Description: 本文将FPGA的快速性和计算机的灵活性通过USB2．0总线有机地结合起来，设计了一个基于FPGA的可调参数FIR滤波系统。此系统由计算机根据各种滤波器指标计算出滤波参数，通过USB2．0对FPGA芯片内部的FIR多阶滤波器进行参数配置，实现数字滤波器参数可调；配置后的FPGA滤波单元完成对A／D采集的信号进行滤波运算，滤波后的数据经过缓存后通过USB2．0总线传输至计算机进行显示、分析和储存等进一步处理。在系统中采用有限状态机对FPGA参数配置模式和滤波模式进行切换，保证了系统的有序运行。-In this dissertation，a reconfigurable FIR filter system based on FPGA is designed，which combine high—speed operation of FPGA and flexibility of computer using USB2．0 interface．According to the filter specialties，the filter coefficients are calculated by the computer．And the configured coefficients of the multistage FIR filter are downloaded to the chip．The filtering computing is completed by the FPGA．The filtered data iS transmitted to the computer through the USB2．0 interface for further processing，such as displaying，analyzing and storing．The states conversion between coefficients configuring mode and filtering mode is finished by FSM(Finite State Machine)，which ensures the system to work orderly．
Platform: | Size: 6375424 | Author: mabeibei | Hits:

[VHDL-FPGA-Verilog] USB2.0IP(RTL)

Description: USB2.0 IP核,ASIC,FPGA可用,Verilog HDL源代码-USB2.0 IP,Verilog HDL
Platform: | Size: 64512 | Author: AmazingEric | Hits:

[VHDL-FPGA-Verilog] usb2.0调试助手

Description: 基于usb2.0的C++上位机，实测可用，仅供参考(USB2.0 based C++ upper computer, measured available, for reference only.)
Platform: | Size: 24762368 | Author: feiyue324 | Hits:
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