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[OtherVedic_Maths

Description: This text book explains briefly about vedic mathematics. which will be very much helpful for fast calculations.
Platform: | Size: 558080 | Author: RUPA KRISHNA | Hits:

[OtherVEDIC-MATHS-for-all

Description: vedic maths for all people
Platform: | Size: 13312 | Author: gambit | Hits:

[OtherVedic_Maths

Description: vedic mathematics e book
Platform: | Size: 558080 | Author: RAJESH | Hits:

[matlabVedicMathsTutorial

Description: it contain vedic maths tutorial to solve maths
Platform: | Size: 47104 | Author: gopi.k | Hits:

[SCMVedic

Description: apprendre les techniques de calcule mentale simle et rapide
Platform: | Size: 1168384 | Author: benq | Hits:

[matlabDesktop

Description: all about vedic mathematics and some matlab files
Platform: | Size: 61440 | Author: sekhar | Hits:

[matlabvedic

Description: all about vedic mathematics and some matlab files
Platform: | Size: 1651712 | Author: sekhar | Hits:

[Documentsfunwithfigures

Description: fun with figures Vedic
Platform: | Size: 809984 | Author: parav | Hits:

[Othernaturalcalc

Description: natural calculator Vedic
Platform: | Size: 46080 | Author: parav | Hits:

[Software Engineeringvedicmuliplier

Description: Vedic multiplier design in Verilog HDL
Platform: | Size: 1024 | Author: pravat | Hits:

[Program docSeriously-Simple-Sums!-Vedic-Maths-ebook

Description: Misc file about maths
Platform: | Size: 112640 | Author: parag | Hits:

[OtherVedic_Maths_Tutorial

Description: a tutorial on vedic maths
Platform: | Size: 47104 | Author: gayu | Hits:

[Industry researchVhdl-Implementation-of--Fast-32x32-Multiplier-Bas

Description: The Vedic mathematics is quite different from conventional method of multiplication like adder and shifter. This mathematics is mainly based on sixteen principles. The multiplier (referred henceforth as Vedic multiplier) architecture based on the URDHVA TIRYAKBHYAM (Vertically and cross wise) sutra is presented. The existing method is 16*16 bit multiplication in relatively less speed. The proposed method is 32*32 bit multiplication in terms of relatively high speed, low power, less area and less delay. This will help in designing multiplier in VHDL, as its give effective utilization of structural method of modelling. This also gives chances for modular design where smaller block can be used to design the bigger one.-The Vedic mathematics is quite different from conventional method of multiplication like adder and shifter. This mathematics is mainly based on sixteen principles. The multiplier (referred henceforth as Vedic multiplier) architecture based on the URDHVA TIRYAKBHYAM (Vertically and cross wise) sutra is presented. The existing method is 16*16 bit multiplication in relatively less speed. The proposed method is 32*32 bit multiplication in terms of relatively high speed, low power, less area and less delay. This will help in designing multiplier in VHDL, as its give effective utilization of structural method of modelling. This also gives chances for modular design where smaller block can be used to design the bigger one.
Platform: | Size: 172032 | Author: farbosein | Hits:

[Printing programvhdl-code-64-bit-vedic

Description: i hope this will help for u
Platform: | Size: 8192 | Author: mgokul177 | Hits:

[Documents2.-Novel-High-Speed-Vedic-Mathematics-Multiplier.

Description: 2. Novel High Speed Vedic Mathematics Multiplier
Platform: | Size: 430080 | Author: chuba | Hits:

[Software Engineeringverilog-code-for-8bit-multiplier-using-vedic-algo

Description: The vedic multiplier is used perform 16 bit multiplication using urdhva tiryakbhyam sutra. this produces the results with high speed and utilizes low power which is most efficient for the real time processors.
Platform: | Size: 11264 | Author: naz | Hits:

[Software Engineeringvedic-multiplier-for-16-bit-input-data

Description: vedic multiplication is used to implement on FPGA. here the vdic multipler uses urdhwa tiryakhbyam sutra to multiply 16 bit numbers, which is applicable for all data type numbers. This uses vertical and cross wise multiplication process. The output results in high speed and low cost for the practical applications.
Platform: | Size: 7168 | Author: naz | Hits:

[VHDL-FPGA-Verilog16x 16 vedic mulbit

Description: vedic 16x16 design and teshbench fully working codes..
Platform: | Size: 5120 | Author: GIRISH | Hits:

[VHDL-FPGA-Verilog32bitvedic and square

Description: 32 bit vedic multiplier documentation
Platform: | Size: 1088512 | Author: vysh | Hits:

[Otherjeas_reversable-vedic-multiplier

Description: reversible logic is mainly used to achieve low power. peres gate HUG gate is used to design a vedic multiplier. reversible gate we can give n numbers of input and we can get n number of output
Platform: | Size: 557056 | Author: paramu | Hits:
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