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Description: This text book explains briefly about vedic mathematics. which will be very much helpful for fast calculations.
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Size: 558080 |
Author: RUPA KRISHNA |
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Description: vedic maths for all people
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Size: 13312 |
Author: gambit |
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Description: vedic mathematics e book
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Size: 558080 |
Author: RAJESH |
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Description: it contain vedic maths tutorial to solve maths
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Size: 47104 |
Author: gopi.k |
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Description: apprendre les techniques de calcule mentale simle et rapide
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Size: 1168384 |
Author: benq |
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Description: all about vedic mathematics and some matlab files
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Size: 61440 |
Author: sekhar |
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Description: all about vedic mathematics and some matlab files
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Size: 1651712 |
Author: sekhar |
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Description: fun with figures Vedic
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Size: 809984 |
Author: parav |
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Description: natural calculator Vedic
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Size: 46080 |
Author: parav |
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Description: Vedic multiplier design in Verilog HDL
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Size: 1024 |
Author: pravat |
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Description: Misc file about maths
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Size: 112640 |
Author: parag |
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Description: a tutorial on vedic maths
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Size: 47104 |
Author: gayu |
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Description: The Vedic mathematics is quite different from
conventional method of multiplication like adder and shifter.
This mathematics is mainly based on sixteen principles. The
multiplier (referred henceforth as Vedic multiplier)
architecture based on the URDHVA TIRYAKBHYAM
(Vertically and cross wise) sutra is presented. The existing
method is 16*16 bit multiplication in relatively less speed. The
proposed method is 32*32 bit multiplication in terms of
relatively high speed, low power, less area and less delay. This
will help in designing multiplier in VHDL, as its give effective
utilization of structural method of modelling. This also gives
chances for modular design where smaller block can be used to
design the bigger one.-The Vedic mathematics is quite different from
conventional method of multiplication like adder and shifter.
This mathematics is mainly based on sixteen principles. The
multiplier (referred henceforth as Vedic multiplier)
architecture based on the URDHVA TIRYAKBHYAM
(Vertically and cross wise) sutra is presented. The existing
method is 16*16 bit multiplication in relatively less speed. The
proposed method is 32*32 bit multiplication in terms of
relatively high speed, low power, less area and less delay. This
will help in designing multiplier in VHDL, as its give effective
utilization of structural method of modelling. This also gives
chances for modular design where smaller block can be used to
design the bigger one.
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Size: 172032 |
Author: farbosein |
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Description: i hope this will help for u
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Size: 8192 |
Author: mgokul177 |
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Description: 2. Novel High Speed Vedic Mathematics Multiplier
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Size: 430080 |
Author: chuba |
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Description: The vedic multiplier is used perform 16 bit multiplication using urdhva tiryakbhyam sutra. this produces the results with high speed and utilizes low power which is most efficient for the real time processors.
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Size: 11264 |
Author: naz |
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Description: vedic multiplication is used to implement on FPGA. here the vdic multipler uses urdhwa tiryakhbyam sutra to multiply 16 bit numbers, which is applicable for all data type numbers.
This uses vertical and cross wise multiplication process.
The output results in high speed and low cost for the practical applications.
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Size: 7168 |
Author: naz |
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Description: vedic 16x16 design and teshbench fully working codes..
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Size: 5120 |
Author: GIRISH
|
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Description: 32 bit vedic multiplier documentation
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Size: 1088512 |
Author: vysh
|
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Description: reversible logic is mainly used to achieve low power. peres gate HUG gate is used to design a vedic multiplier. reversible gate we can give n numbers of input and we can get n number of output
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Size: 557056 |
Author: paramu |
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