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[SCM] oc8051

Description: 51的VERILOG代码！适用于Xilinx的FPGA-51 VERILOG code! In Xilinx FPGA
Platform: | Size: 1220608 | Author: 林建加 | Hits:

[ARM-PowerPC-ColdFire-MIPS] ARM_Core

Description: arm verilog hdl ip core-arm Verilog HDL core ip
Platform: | Size: 70656 | Author: lile | Hits:

[VHDL-FPGA-Verilog] adma

Description: Wishbone dma ip core
Platform: | Size: 7168 | Author: liwen | Hits:

[Other] HowtosimulateIPCore

Description: IP核生成器生成 ip 后有两个文件对我们比较有用，假设生成了一个 asyn_fifo 的核，则 asyn_fifo.veo 给出了例化该核方式（或者在 Edit－>Language Template->COREGEN 中找到 verilog/VHDL 的例化方式）。asyn_fifo.v 是该核的行为模型，主要调用了 xilinx 行为模型库 的模块，仿真时该文件也要加入工程。-IP core generator generate ip after two documents more useful to us. Formation of a hypothetical nuclear asyn_fifo, asyn_fifo.veo were given cases of the methods (or Edit-
Platform: | Size: 359424 | Author: 任学 | Hits:

[VHDL-FPGA-Verilog] my_ip_core

Description: 在quartusII下用verilog语言自己写的IP核，对FPGA开发初学者有帮助的。-in quartusII verilog using their own language to write the IP core, FPGA development beginners to help.
Platform: | Size: 51200 | Author: 刘海 | Hits:

[VHDL-FPGA-Verilog] ip_fft128

Description: 128点fft的IP核vhdl源代码，另有其控制代码。-128 point fft s IP core VHDL source code, while its control code.
Platform: | Size: 7168 | Author: 戈立军 | Hits:

[VHDL-FPGA-Verilog] Ethernet_verilog_ip_core

Description: Ethernet(以太网)verilog ip core用verilogHDL语言写的以太网软核，对学习verilog语言和以太网有很大帮助。-Ethernet (Ethernet) verilog ip core language used verilogHDL Ethernet soft-core, learning Verilog language and Ethernet are very helpful.
Platform: | Size: 903168 | Author: houlongting | Hits:

[VHDL-FPGA-Verilog] 8255

Description: Verilog语言描述的Intel8255 IP Core，本人已经在某项目中经过了物理验证的，可直接用于FPGA综合或ASIC综合。
Platform: | Size: 6144 | Author: David.Mr.Liu | Hits:

[Other] EHERNETIPcore

Description: 该文件包含以太网IP核的相关代码，一共包含24个VERILOG源代码-This document contains the relevant Ethernet IP core code, a total of 24 includes Verilog source code
Platform: | Size: 69632 | Author: season | Hits:

[VHDL-FPGA-Verilog] SRAM_16Bit_512K

Description: Verilog 编写的IP核，512K的16位SRAM-Written in Verilog IP core, 512K 16-bit SRAM
Platform: | Size: 11264 | Author: zhyy | Hits:

[VHDL-FPGA-Verilog] DM9000A

Description: Verilog 编写的网卡DM9000A的IP核，altera公司寄的DE2系统中的源程序核-Verilog prepared DM9000A the IP core network card, altera company sent DE2 System source of nuclear
Platform: | Size: 16384 | Author: zhyy | Hits:

[Other Embeded program] cyc2_cmon_080805

Description: Verilog 8051 IP Core for Cyclone -Verilog 8051 IP Core for Cyclone II
Platform: | Size: 63488 | Author: Alx | Hits:

[Crack Hack] aes_core

Description: aes_core verified verilog ip core-aes_core verified verilog ip core
Platform: | Size: 11264 | Author: 邓婕 | Hits:

[ARM-PowerPC-ColdFire-MIPS] arm7verilog

Description: ARM 7 免费ip 核， verilog语言描述-arm7 free ip core, verilig DHL
Platform: | Size: 1400832 | Author: zdh | Hits:

[Embeded-SCM Develop] ARMcore

Description: 基于FPGA的ARM IP核！该软核VHDL源码全部开放-FPGA-based ARM IP core! The soft core VHDL source code are all open
Platform: | Size: 690176 | Author: 王钊 | Hits:

[VHDL-FPGA-Verilog] sd_slave_device

Description: verilog source code for SD card SLAVE DEVICE IP-Core
Platform: | Size: 15360 | Author: Antti Lukats | Hits:

[VHDL-FPGA-Verilog] pipelined_fft_64

Description: 利用IP Core编写的Verilog程序，实现FFT变换，希望对大家有帮助。-Written using Verilog IP Core procedures to achieve FFT transformation, we want to help.
Platform: | Size: 99328 | Author: chengyungang | Hits:

[VHDL-FPGA-Verilog] wishbone

Description: wishbone IP CORE Verilog quartus-wishbone IP CORE Verilog quartusii
Platform: | Size: 13312 | Author: thegreeneyes | Hits:

[VHDL-FPGA-Verilog] ethernet10-100M-IP-core

Description: 以太网10-100M IP核Verilog源码，可综合-Ethernet 10-100M IP core Verilog source code can be integrated
Platform: | Size: 740352 | Author: owen | Hits:

[VHDL-FPGA-Verilog] verilog-ip-core

Description: verilog ip核，源代码，ethernet， video_compression_systems-verilog ip core source code, ethernet, video_compression_systems
Platform: | Size: 3798016 | Author: 刘兵 | Hits:
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