Search - verilog PCI

[Embeded-SCM Develop] pcit32_lattice

Description: PCI接口的Verilog源代码-PCI connection Verilog source code
Platform: | Size: 397312 | Author: 包盛花 | Hits:

[Documents] PCI系统结构

Description: 卓越写的PCI系统结构-excellence write PCI System
Platform: | Size: 121856 | Author: 卓越 | Hits:

[Books] Addison.Wesley.PCI.Express.System.Architecture.eBo

Description: Pci Express系统结构电子书-system structure by taking PCI Express e-books
Platform: | Size: 13181952 | Author: 卓越 | Hits:

[Embeded-SCM Develop] 1091516677

Description: PCI总线仲裁参考设计Verilog代码-PCI bus arbitration reference design Verilog code
Platform: | Size: 3072 | Author: 熊熊 | Hits:

[VHDL-FPGA-Verilog] PCI总线仲裁参考设计，Quicklogic提供

Description: PCI总线仲裁参考设计，Quicklogic提供的verilog代码-PCI bus arbitration reference design, pioneered the Verilog code
Platform: | Size: 3072 | Author: 陈旭 | Hits:

[Other Embeded program] pcit32_verilog_lattice

Description: 本文件是pci的verilog源代码程序-pci the Verilog source code procedures
Platform: | Size: 430080 | Author: 王立华 | Hits:

[VHDL-FPGA-Verilog] pcirtl

Description: 用verilog编写的pci——rtl级。-using Verilog prepared by the pci-- rtl level.
Platform: | Size: 197632 | Author: 程 | Hits:

[Other] PCI_Target_ip

Description: pci core altera fpga pci开发设计资料-pci core altera fpga development of design information pci
Platform: | Size: 428032 | Author: zhouhong | Hits:

[ELanguage] usb_funct

Description: USB接口的VHDL源码，支持Verilog HDL程序-USB VHDL source code, supports Verilog HDL procedures
Platform: | Size: 230400 | Author: 王森 | Hits:

[VHDL-FPGA-Verilog] pci_verilog

Description: 一个pci接口的硬件描述语言的实现源代码,用verilog语言实现-a pci interface hardware description language source code to achieve with verilog language
Platform: | Size: 428032 | Author: 大为 | Hits:

Description: 这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序，用verilog实现，ise7.1，不知道这里可不可以上传硬件的程序~-pci-wishbone nuclear and nuclear Serial 16,450 in the TP xilinx They achieved a serial program, verilog realization ise7.1. Can here do not know the procedures upload hardware ~
Platform: | Size: 8427520 | Author: heartbeat | Hits:

[MPI] pci_core_verilog

Description: PCI-master的核，verilog语言，经测试，可完成芯片的综合及布线-PCI-master s nuclear, verilog language, by testing, to be completed by the integrated chip and wiring
Platform: | Size: 216064 | Author: 伊路发 | Hits:

[VHDL-FPGA-Verilog] pci

Description: pci接口的verilog原代码,定义了pci接口所需要的全部引脚-pci interface Verilog source code, the definition of a pci interface pins required by all
Platform: | Size: 4096 | Author: david | Hits:

[VHDL-FPGA-Verilog] tstbench

Description: pci 接口协议用Verilog编写，经过测试使用，与大家共享-pci interface protocol using Verilog prepared, tested the use, and share
Platform: | Size: 15360 | Author: hanbing | Hits:

[Other] PCI

Description: PCI设计指南The Xilinx LogiCORE PCI interface is a fully verified, pre-implemented PCI Bus interface. This interface is available in 32-bit and 64- bit versions, with support for multiple Xilinx FPGA device families. It is designed to support both Verilog-HDL and VHDL. The design examples in this book are provided in Verilog.-PCI Design Guide The Xilinx LogiCORE PCI interface is a fully verified, pre-implementedPCI Bus interface. This interface is available in 32-bit and 64-bit versions, with support for multiple Xilinx FPGA device families. Itis designed to support both Verilog-HDL and VHDL. The designexamples in this book are provided in Verilog.
Platform: | Size: 899072 | Author: lee | Hits:

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[Embeded-SCM Develop] pcit32_lattice

[Documents] PCI系统结构

[Books] Addison.Wesley.PCI.Express.System.Architecture.eBo

[Embeded-SCM Develop] 1091516677

[VHDL-FPGA-Verilog] PCI总线仲裁参考设计，Quicklogic提供

[Other Embeded program] pcit32_verilog_lattice

[VHDL-FPGA-Verilog] pcirtl

[Other] PCI_Target_ip

[ELanguage] usb_funct

[VHDL-FPGA-Verilog] pci_verilog

[Other] PCI_Bridge_Guest_UART

[MPI] pci_core_verilog

[VHDL-FPGA-Verilog] pci

[VHDL-FPGA-Verilog] tstbench

[Other] PCI

[Other] lpcinterface

[Embeded-SCM Develop] cpld-pci

[Embeded-SCM Develop] FPGA-PCI

[USB develop] pci-verilog

[VHDL-FPGA-Verilog] Verilog-pci

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