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这是北大的Verilog讲义,PPT,初学者,可以看看.
Update : 2008-10-13 Size : 257.28kb Publisher : 大金湖

Verilog HDL语言的PPT教程。包括简介、逻辑概念、语法和示例。
Update : 2008-10-13 Size : 523.77kb Publisher : 翟红光

北航夏宇闻verilog讲稿ppt-Northern Xia Wen Verilog script ppt
Update : 2025-02-17 Size : 499kb Publisher : 陈平

verilog数字系统设计教程 所有例题的源程-Verilog Digital System Design Guide examples of all-source
Update : 2025-02-17 Size : 541kb Publisher : 丁强

经典的verilog语言学习课件,介绍了语言的基础知识,和实际中该语言的应用包括DSP 设计中的各个方面.-classic Verilog language-learning courseware, introduced a basic knowledge of language, and the reality of the language of applications including DSP design in all its aspects.
Update : 2025-02-17 Size : 3.75mb Publisher : hcf2005

华为内部的verilog教材的ppt版本。比较详细。-Huawei internal verilog materials ppt version. More detailed.
Update : 2025-02-17 Size : 256kb Publisher : rain6537

DL : 0
包含北航夏宇闻写《verilog数字系统设计》中的所有代码-XIA Yu-Wen wrote BUAA contains verilog digital system design, all of the code
Update : 2025-02-17 Size : 279kb Publisher : zjy

这是北大的Verilog讲义,PPT,初学者,可以看看.-This is the Beijing University of Verilog lectures, PPT, beginners can take a look at.
Update : 2025-02-17 Size : 257kb Publisher : 大金湖

DL : 1
一个介绍verilog HDL的ppt文档,包括全部的22章。-Verilog HDL a presentation of ppt documents, including all of Chapter 22.
Update : 2025-02-17 Size : 1.48mb Publisher : 林熙鹏

DL : 1
Verilog HDL语言的PPT教程。包括简介、逻辑概念、语法和示例。-Verilog HDL language tutorial PPT. Including profiles, the logic of concepts, syntax and examples.
Update : 2025-02-17 Size : 524kb Publisher : 翟红光

verilog超详细的教程 数字集成电路设计入门--从HDL到版图,北大微电子学系,于敦山 ppt-Ultra-detailed tutorials Verilog digital IC design entry to the territory from the HDL, the Department of Microelectronics, Peking University, in mts ppt
Update : 2025-02-17 Size : 1.48mb Publisher : 文成

数字集成电路设计入门 --从HDL到版图 于敦山 北大微电子学系 Verilog完整课件,是学习verilog HDL的很好的参考资料。 -Introduction to digital integrated circuit design- from the territory in HDL mts Microelectronics Department of Beijing University Verilog complete courseware, learning verilog HDL is a good reference.
Update : 2025-02-17 Size : 614kb Publisher : hulin

上海大学 Verilog PPT 适合初学者看 推荐 -Shanghai University Verilog PPT look recommended for beginners
Update : 2025-02-17 Size : 2.37mb Publisher : ly

DL : 0
北航夏宇闻verilog讲稿ppt,包括语法入门、语法进阶及多种实例,Verilog仿真工具-Xia Wen BUAA Verilog script ppt, including the entry syntax, grammar and a variety of advanced examples, Verilog simulation tool
Update : 2025-02-17 Size : 502kb Publisher : zx

verilog语言的北大教材。PPT格式,比较详细-North Verilog language teaching materials. PPT format, a more detailed
Update : 2025-02-17 Size : 249kb Publisher : JoeYounG

verilog语言的北大教材。PPT格式,比较详细-North Verilog language teaching materials. PPT format, a more detailed
Update : 2025-02-17 Size : 365kb Publisher : JoeYounG

verilog语言的北大教材。PPT格式,比较详细-North Verilog language teaching materials. PPT format, a more detailed
Update : 2025-02-17 Size : 414kb Publisher : JoeYounG

verilog语言的北大教材。PPT格式,比较详细-North Verilog language teaching materials. PPT format, a more detailed
Update : 2025-02-17 Size : 108kb Publisher : JoeYounG

北航夏宇闻verilog讲稿ppt语法入门-Wen Yu Xia Beihang verilog script syntax entry ppt
Update : 2025-02-17 Size : 50kb Publisher : 王军

一个很好的关于verilog的PPT 第1章 EDA设计与Verilog HDL语言概述 第2章 Verilog HDL基础与开发平台操作指南 第3章 Verilog HDL程序结构 第4章 VERILOG HDL语言基本要素 第5章 面向综合的行为描述语句 第6章 面向验证和仿真的行为描述语句 第7章 系统任务和编译预处理语句 第8章 VERILOG HDL可综合设计的难点解析 第9章 高级逻辑设计思想与代码风格 第10章 可综合状态机开发实例 第11章 常用逻辑的VERILOG HDL实现 第12章 XILINX硬核模块的VERILOG HDL调用 第13章 串口接口的VERILOG HDL设计-A good verilog of PPT on Chapter 1 of EDA Design and Verilog HDL language outlined in Chapter 2 based on Verilog HDL and development platform Operations Guide Chapter 3 Verilog HDL program structure VERILOG HDL languages Chapter 4 Chapter 5 for the basic elements of an integrated behavioral description statement in Chapter 6 for the verification and simulation of the behavior of the system described in Chapter 7 mission statements and prepared statements compiled in Chapter 8 VERILOG HDL design can be integrated Difficulties in Chapter 9, advanced logic design and coding style Chapter 10 Comprehensive state machine instance can be developed in Chapter 11 to achieve common logic VERILOG HDL Chapter 12 XILINX hard core module VERILOG HDL called Chapter 13 Serial Interface VERILOG HDL design
Update : 2025-02-17 Size : 26.54mb Publisher : lyy
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