Search - verilog UART

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[VHDL-FPGA-Verilog] micro uart DL : 0: 硬件uart源程序verilog HDL，即相关文档-hardware UART Verilog HDL source, that the relevant documents
Update : 2025-02-17 Size : 335kb Publisher : 陈正一
[Communication] verilog for uart DL : 0: 通用异步接收器/发送器(UART)是能够编程以控制计算机到附加串行设备的接口的微芯片。详细来说,它提供给计算机RS-...还有高级的UART提供了一定数量的数据缓冲,这样计算机和串行设备数据流就可以保持同样的速度。-universal asynchronous receiver/transmitter (UART) can be programmed to control computer attached to the serial device interface microchips. Details, provide it to the computer RS-High ... UART also provide a certain number of data buffer, computer equipment and serial data stream can maintain the same speed.
Update : 2025-02-17 Size : 9kb Publisher : 李志
[VHDL-FPGA-Verilog] u-uart DL : 0: 一个可综合的串并转换接口verilog源代码-a comprehensive series of conversion and interface Verilog source code
Update : 2025-02-17 Size : 5kb Publisher : 李文文
[VHDL-FPGA-Verilog] uart-verilog-vhdl DL : 0: 拿verilog和vhdl编写的串口通信代码(可综合)-with vhdl and verilog prepared by the serial communication code (synthesis)
Update : 2025-02-17 Size : 288kb Publisher : 刘索山
[VHDL-FPGA-Verilog] uart_core_vhdlORverilog DL : 0: 串uart的vhdl，verilog，lattic实现原码里面有四个文件,分别UART 源码 (lattice version)\uart 源码 (Verilog)\uart 源码 (VHDL)\uart16550.tar-uart series of vhdl and verilog. lattic achieve the original code, there are four documents, Source respectively UART (lattice version) \ uart source (Verilog) \ uart source (VHDL) \ uart16550.tar
Update : 2025-02-17 Size : 288kb Publisher : efly
[Other Embeded program] uart DL : 0: 实现简单的UART功能,在QUARTUS4.0下编译通过,采用VERILOG HDL编写.-Simple UART functions in the compiler under QUARTUS4.0 through using VERILOG HDL preparation.
Update : 2025-02-17 Size : 1kb Publisher : 不是
[VHDL-FPGA-Verilog] UART DL : 0: UART 串口程序，verilog语句，很好的实现了UART的通信功能！-UART serial procedures, verilog statement, very good communication to achieve the UART function!
Update : 2025-02-17 Size : 178kb Publisher : 王和国
[VHDL-FPGA-Verilog] uart DL : 0: 用Verilog实现的串口异步通信，适用于RS232-Using Verilog realization of serial asynchronous communication, applied to RS232
Update : 2025-02-17 Size : 1.07mb Publisher : 王权
[Com Port] uart DL : 0: this a Uart source code using Verilog.
Update : 2025-02-17 Size : 10kb Publisher : Daniel Zhang
[VHDL-FPGA-Verilog] UART DL : 0: verilog设计的UART事例，适合于初学者-Verilog UART design examples, suitable for beginners
Update : 2025-02-17 Size : 151kb Publisher : 张扬
[Com Port] uart DL : 0: 采用CPLD实现串口通信（Verilog硬件描述语言）-Realize the use of CPLD serial communication (Verilog Hardware Description Language)
Update : 2025-02-17 Size : 5kb Publisher : wuzhidong
[Com Port] uart(Verilog) DL : 0: RS232的verilog源代码,如果需要的可以-RS232 of Verilog source code, if necessary can be
Update : 2025-02-17 Size : 10kb Publisher : 陈强
[VHDL-FPGA-Verilog] uart(Verilog) DL : 0: uart异步串口通信协议的源代码，用vhdl语言编写，并且有完整得测试文件-UART asynchronous serial communication protocol source code, using VHDL language, and may have a complete test file
Update : 2025-02-17 Size : 10kb Publisher : 阿军
[Other] u-uart DL : 0: UART verilog TX/RX OpenCores share
Update : 2025-02-17 Size : 5kb Publisher : richman
[VHDL-FPGA-Verilog] UART DL : 0: 串口通讯 verilog CPLD EPM1270 源代码-Serial Communication verilog CPLDEPM1270 source code
Update : 2025-02-17 Size : 55kb Publisher : 韩思贤
[VHDL-FPGA-Verilog] mini-uart DL : 0: Verilog实现mini-uart，代码经过FPEG验证，含文档及流程图。-Verilog implementation mini-uart, code FPEG After verification, including documentation and flow chart.
Update : 2025-02-17 Size : 248kb Publisher : serein
[Other Embeded program] UART DL : 0: 主芯片：Actel的FPGA030,Verilog语言,串口发送和接收的例程，开发环境：LiberoIDE 8.5-The main chip: Actel' s FPGA030, Verilog language, the serial port to send and receive routines, development environment: LiberoIDE 8.5
Update : 2025-02-17 Size : 279kb Publisher : grqd
[VHDL-FPGA-Verilog] uart DL : 0: Verilog编写的UART程序源代码。测试成功。支持字符串发送-UART prepared Verilog source code. Successful test. Support string sent
Update : 2025-02-17 Size : 1.48mb Publisher : 卢山
[Com Port] UART DL : 0: 利用Verilog实现一个UART接口，包含三个源文件rcvr.v\txmit.v\uart.v -Verilog realization of the use of a UART interface, the source file contains three rcvr.v \ txmit.v \ uart.v
Update : 2025-02-17 Size : 2kb Publisher : speed
[VHDL-FPGA-Verilog] uart DL : 0: verilog编写的uart发送和接收的源代码。简单易懂。-verilog uart prepared to send and receive the source code. Straightforward.
Update : 2025-02-17 Size : 468kb Publisher : luoqv

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