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[VHDL-FPGA-Verilog] adder

Description: 加法器（使用verilog编写的）,虽然简单，但是这也是学习verilog最基础的东西！希望大家一起学习！-The accumulator (uses the verilog compilation), although it is simple, but this also is studies most foundation of the verilog! Hopes everybody studies together!
Platform: | Size: 134144 | Author: | Hits:

[VHDL-FPGA-Verilog] adder16bit

Description: 16位高速加法器，采用verilog语言编写，已经成功仿真，能够运行-16 high-speed adder using Verilog language has been successful simulation can be run
Platform: | Size: 2048 | Author: modelsims | Hits:

[VHDL-FPGA-Verilog] CORDIC01

Description: CORDIC算法的硬件实现 用的verilog语言-CORDIC algorithm Hardware Implementation of the Verilog language
Platform: | Size: 221184 | Author: 李文文 | Hits:

[VHDL-FPGA-Verilog] add_16_pipe

Description: 16位加法器的流水线计算,verilog代码，用于FPGA平台。-16 pipelined adder, verilog code for the FPGA platform.
Platform: | Size: 1024 | Author: qjyong | Hits:

[Embeded-SCM Develop] verilog.HDL.examples

Description: 许多非常有用的 Verilog 实例: ADC, FIFO, ADDER, MULTIPLIER 等-many very useful Verilog examples : ADC, FIFO, ADDER, MULTIPLIER etc.
Platform: | Size: 188416 | Author: 张驰 | Hits:

[Other Embeded program] adder

Description: 基于ALTERA 公司cyclone系列FPGA的程序，verilog 实现加法器-ALTERA company based FPGA family of cyclone procedures, verilog adder realize
Platform: | Size: 209920 | Author: 陶德杰 | Hits:

[VHDL-FPGA-Verilog] vhdlsource

Description: 用verilog hdl编写的一些例程，包括加法器/减法器等等，例子较多就不一一列举了-Verilog hdl prepared with some routines, including the adder/subtraction, etc., for example, more is not to enumerate the
Platform: | Size: 4096 | Author: 刘念洲 | Hits:

[VHDL-FPGA-Verilog] adder4

Description: verilog加法器,附加测试文件 可用modelsim 仿真实现-Verilog Adder, additional test file ModelSim simulation can be used to achieve
Platform: | Size: 5120 | Author: luminous | Hits:

[Other] FULLADD

Description: Full adder using Verilog
Platform: | Size: 11264 | Author: ying chen | Hits:

[VHDL-FPGA-Verilog] fadd

Description: 6级流水，verilog实现浮点数的加法，其中浮点数格式符合IEEE754标准-6 water, verilog realize the floating point adder, in which floating-point format in line with the IEEE754 standard
Platform: | Size: 2048 | Author: 兰兰 | Hits:

[VHDL-FPGA-Verilog] adder4

Description: 是用verilog写得加法器以及计数器里面有测试文件（testbench），对于初学者来说这个可以用来参考下-Is written in Verilog adder and counter inside a test file (testbench), for beginners this can be used to reference the next
Platform: | Size: 1024 | Author: olive | Hits:

[VHDL-FPGA-Verilog] Mars_EP1C6F_Fundermental_demo(Verilog)

Description: FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。-FPGA development board supporting Verilog HDL code. Chips for the Mars EP1C6F. Are the basic source experiment. Including the adder, subtraction, and multiplier, such as MUX.
Platform: | Size: 1244160 | Author: chenlu | Hits:

[VHDL-FPGA-Verilog] adder

Description: FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
Platform: | Size: 1024 | Author: surya | Hits:

[VHDL-FPGA-Verilog] adder

Description: verilog for full_adder
Platform: | Size: 1024 | Author: max | Hits:

[VHDL-FPGA-Verilog] adder

Description: verilog 加法器设计 在modelsim下方针-verilog adder
Platform: | Size: 1039360 | Author: 兰书明 | Hits:

[VHDL-FPGA-Verilog] cascaded_adder

Description: implementation of cascade adder with verilog plus testbench
Platform: | Size: 4096 | Author: shabnam | Hits:

[VHDL-FPGA-Verilog] verilog

Description: verilog语言例题集锦 包含加法器，乘法器，串并转换器等verilog源代码-Example Collection contains verilog language adder, multiplier, and converters, such as string verilog source code
Platform: | Size: 113664 | Author: 刘佳扬 | Hits:

[Energy industry] Verilog

Description: 全加器的Verilog 实现代码 寄存器的Verilog 实现代码-Low-pass filter integral part of full-adder and register the Verilog implementation code
Platform: | Size: 3072 | Author: 田静 | Hits:

[VHDL-FPGA-Verilog] Floating-Point-Adder

Description: 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmable technology, complete with 5 line-stage pipeline structure to meet IEEE 754 floating point standards, parameters into a single, double precision floating point adder.
Platform: | Size: 154624 | Author: 凌音 | Hits:

[VHDL-FPGA-Verilog] 64B_adder

Description: Verilog HDL 64位并行加法器,并且还含有测试文件，可供测试-Verilog HDL 64-bit parallel adder, and also contains a test file, ready for testing
Platform: | Size: 1024 | Author: xxz | Hits:
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