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Description: 里面包含大量由浅入深的verilog code,欢迎下载
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Size: 105373 |
Author: 312589762@qq.com |
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Description: Verilog编码与综合中的非阻塞性赋值-Verilog code and synthesis must blocking evaluation
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Size: 52224 |
Author: 徐路 |
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Description: 曼彻斯特编解码Verilog代码 .zip-Manchester codec Verilog code. Zip
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Size: 10240 |
Author: 崔广辉 |
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Description: verilog实现ALU的源代码,并提供了一个详细的测试平台!-achieve ALU Verilog source code, and provide a detailed test platform!
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Size: 1024 |
Author: 飞扬 |
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Description: Arm9指令Cache缓存模块的verilog代码,对一些做ARM硬件开发的朋友有参考价值。-Arm9 Instruction Cache Cache Module Verilog code, do some of the hardware development of the ARM friends reference value.
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Size: 3072 |
Author: 杨力 |
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Description: FIR FILTER verilog code-FIR FILTER Verilog code
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Size: 26624 |
Author: QQ |
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Description: 这是arm7处理器的verilog全代码,仔细研究一下,会对CPU和verilog均有很大的裨益。-This is ARM7 processor Verilog-wide code carefully, CPU and Verilog will have great benefits.
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Size: 37888 |
Author: 王云 |
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Description: 利用FPGA实现浮点运算的verilog代码
希望能够给需要做这方面研究的同仁有所帮助-use FPGA floating-point operations verilog code hope to be able to do this to the need for research in the Tongren help
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Size: 130048 |
Author: jake |
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Description: 16位加法器的流水线计算,verilog代码,用于FPGA平台。-16 pipelined adder, verilog code for the FPGA platform.
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Size: 1024 |
Author: qjyong |
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Description: 此是进行循环冗余效验的Verilog编码,适合多种标准,如CRC16-this Cyclic Redundancy is well-tested Verilog code for a variety of criteria, such as CYXLIC REDUNDANCY
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Size: 3072 |
Author: 藏瑞 |
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Description: 拿verilog和vhdl编写的串口通信代码(可综合)-with vhdl and verilog prepared by the serial communication code (synthesis)
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Size: 294912 |
Author: 刘索山 |
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Description: jpeg压缩中的DCT蝶型算法verilog代码-jpeg DCT compression algorithm verilog code BUTTERFLY
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Size: 5120 |
Author: wuguanying |
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Description: 用verilog代码写的JPEG压缩核心模块DCT变换之蝶形单元算法-verilog code written using JPEG compression core module DCT's butterfly modules algorithm
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Size: 1024 |
Author: 叶人杰 |
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Description: VHDL和Verilog代码互转工具,对EDA工程人员会有很大的帮助.-VHDL and Verilog code referrals tools, EDA staff to be very helpful.
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Size: 3962880 |
Author: 张华 |
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Description: 4×4键盘扫描的verilog 代码,在CPLD板上实现-4 × 4 keyboard scan Verilog code, the CPLD on the board realize
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Size: 1024 |
Author: fang zhou |
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Description: 一个好用的经过FPGA验证的i2c_slave verilog代码。-After a useful FPGA proven i2c_slave verilog code.
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Size: 4096 |
Author: 王晓琴 |
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Description: sdram的控制器 verilog源码-SDRAM controller Verilog source code
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Size: 718848 |
Author: 唐业衡 |
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Description: 用verilog写的仿ARM7的代码,在opencore上,现在被撤掉了-Written by verilog code like ARM7
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Size: 37888 |
Author: stream |
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Description: Image processing binarisation verilog code
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Size: 308 |
Author: spgp1306 |
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Description: Basic Verilog code includes RING and Johnson counters, Up-down counters, RAM, ROM, SIPO, PISO, SISO, PIPO, Mealy and Moore FSM codes
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Size: 9386 |
Author: spgp1306 |
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