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[VHDL-FPGA-Verilog] div2

Description: 32位除法器 被除数和除数均为16位整数，16位小数 商为32位整数，16位小数 余数为16位整数，16位小数 Verilog HDL 代码-32 divider dividend and divisor are 16-bit integer, decimal 16 for the 32-bit integer, 16-bit decimal number more than 16 integer, 16-bit decimal Verilog HDL code
Platform: | Size: 1024 | Author: 李春阳 | Hits:

[VHDL-FPGA-Verilog] divide

Description: 除法器的设计本文所采用的除法原理是：对于八位无符号被除数A，先对A转换成高八位是0低八位是A的数C，在时钟脉冲的每个上升沿C 向左移动一位，最后一位补零，同时判断C的高八位是否大于除数B，如是则C的高八位减去B，同时进行移位操作，将C的第二位置1。否则，继续移位操作。经过八个周期后，所得到的C的高八位为余数，第八位为商。从图(1)可清楚地看出此除法器的工作原理。此除法器主要包括比较器、减法器、移位器、控制器等模块。-Divider design used in this paper, the principle of division is: For the eight unsigned dividend A, the first of A into the high-low 8 0 8 is the A number of C, in each clock rising edge to the left C Mobile One, and finally a zero, at the same time to determine whether C is greater than the high-8 divisor B, so is the high C 8 minus B, at the same time shift operation, the location will be C s second one. Otherwise, continue to shift operation. After eight cycles, received a high C for more than eight the number of eighth place for the business. From Figure (1) can clearly see that the divider works. This mainly includes divider comparators, subtraction, and shifter, controller modules.
Platform: | Size: 1024 | Author: lyy | Hits:

[VHDL-FPGA-Verilog] 32divider

Description: 32位元2進位除法器 -32-bit binary divider 2
Platform: | Size: 2048 | Author: chen | Hits:

[VHDL-FPGA-Verilog] verilogfenpinqi

Description: verilog分频器代码 分为偶数倍分频和奇数倍分频两个verilog源文件 附带一个说明文档-divider verilog code for multiple sub-divided into even and odd frequency divider several times with a two verilog source files documentation
Platform: | Size: 2048 | Author: 王楚宏 | Hits:

[VHDL-FPGA-Verilog] v

Description: Verilog写的二分频电路代码，FPGA，实现将输入时钟信号的频率变成原来的1/2-Write Verilog code for the second divider circuit, FPGA, to achieve the frequency of the input clock signal into the original 1/2
Platform: | Size: 6144 | Author: wudong | Hits:

[VHDL-FPGA-Verilog] combinational_divider

Description: 参数可配置的除法器verilog源代码，验证通过-verilog soure code for divider with configurable parameters
Platform: | Size: 1024 | Author: shuanghx | Hits:

[VHDL-FPGA-Verilog] divider_32bitdivby16bit

Description: verilog代码实现的32位除以16位无符号整数除法器，在别人8位除法器的基础上改进完成，32个时钟周期完成一次运算。-verilog code for 32-bit divided by 16-bit unsigned integer divider it s based on other guy s 8 bit divider verilog code. it need 32 clock cycles to complete an operation.
Platform: | Size: 1024 | Author: jiang | Hits:

[Other Embeded program] fen-pin-Verilog(2013-06-25-09.54.41)

Description: 任意小数分频，适用于对精确度要求不高的代码中-Any fractional divider, suitable for less demanding precision code
Platform: | Size: 6144 | Author: 李南 | Hits:

[VHDL-FPGA-Verilog] DIVIDER

Description: M进制计数器 verilog code for divider-verilog code for divider verilog code for dividerverilog code for divider
Platform: | Size: 2048 | Author: HP | Hits:

[VHDL-FPGA-Verilog] CLK_div

Description: 用verilog写的分频器，包括16分频，8分频，4分频，2分频等，代码简单，效率高，个人感觉很实用且对初学者很有帮助-Written in verilog divider, including 16 points frequency, frequency eight points, 4 points frequency, frequency division 2, etc., the code is simple, high efficiency, personal feeling is very practical and is very helpful for beginners
Platform: | Size: 1024 | Author: 张俊 | Hits:

[Other] streamline_div

Description: 一个资源很省的乘法器,代码为Verilog代码,8位除法器，除法结果在8个时钟后输出.代码也可自行扩展到更大位宽.-A resource is the province of the multiplier, code for Verilog code, 8-bit divider, division results in eight clock output. Code can also extend themselves to greater width.
Platform: | Size: 1024 | Author: Andy Zhou | Hits:

[VHDL-FPGA-Verilog] FPGA__source-code__Verilog

Description: FPGA部分基础功能源代码，适合初学者进行学习仿真，代码可读性强，通俗易懂，逻辑清晰。包括触发器，全加器，分频，并串转换，计数器，序列发生器等Verilog语言源代码。- Part of the basic functions of the source code for FPGA.Suitable for beginners to learn the simulation, the code readable, easy to understand, clear logic. Including triggers, full adder, divider, and parallel to serial conversion, counter, sequencer and other Verilog language source code.
Platform: | Size: 1908736 | Author: 张秋爽 | Hits:

[VHDL-FPGA-Verilog] divider1-(3)

Description: Code for divider is written in Verilog where divider and dividend both are of 8 bits. Division is done using continuous subtraction method until the divisor becomes greater or equal to dividend.
Platform: | Size: 1024 | Author: bcd | Hits:

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