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[VHDL-FPGA-Verilog] 8bitsine

Description: 8bit采样sine波形发生器,一共两个文件，各自用VHDL和VERILOG编写，通信开发平台专用-8bit sampling sine wave generator, a total of two papers, each with VHDL and VERILOG preparation, communications development platform dedicated
Platform: | Size: 5120 | Author: 王刚 | Hits:

[VHDL-FPGA-Verilog] rom

Description: Read-only memory,Verilog code
Platform: | Size: 8192 | Author: leigh lee | Hits:

[Other Embeded program] verilog_sin_complete

Description: verilog设计正弦波波形模块,可自己通过参数设置得到所需峰值的波形-Verilog design module sinusoidal waveform can be themselves through the necessary parameters of the waveform peak
Platform: | Size: 3072 | Author: 刘彬 | Hits:

[VHDL-FPGA-Verilog] rom

Description: 一个 16×8bit 的ROM程序包括程序的初始化。-A 16 × 8bit the ROM initialization procedures, including procedures.
Platform: | Size: 3072 | Author: h13978699183 | Hits:

[VHDL-FPGA-Verilog] sine

Description: Verilog编程，利用FPGA实现两路正弦波的信号输出，也可以扩展成六路正弦输出-Verilog programming, the use of FPGA realize two sinusoidal output signals can also be extended into a six-way sinusoidal output
Platform: | Size: 4792320 | Author: 陈剑 | Hits:

[VHDL-FPGA-Verilog] rom

Description: 我用VHDL写的正弦，用FPGA内部ROM，有仿真testbench,在quartus里可以运行。在板子里已经验证-I used to write VHDL sinusoidal, using FPGA internal ROM, has simulation testbench, you can run in Quartus. Yard has already been verified in the plates
Platform: | Size: 651264 | Author: jimmy | Hits:

[VHDL-FPGA-Verilog] RAM_Examples

Description: Verilog hdl code for representing ram and rom "memory" using many methods
Platform: | Size: 5120 | Author: Muftah | Hits:

[SCM] rom

Description: Rom的读取的Verilog代码，自己编写的，大家参考参考啊-Rom read the Verilog code, I have written, your information ah
Platform: | Size: 1024 | Author: keke | Hits:

[VHDL-FPGA-Verilog] SPI_controller

Description: SPI serial flash ROM的verilog源代码, 针对winbond W25x16,已经经过逻辑验证,并实际用在芯片设计中,作为一个模块,正常工作.-SPI serial flash ROM in verilog source code for winbond W25x16, logic has been verified, and actually used in chip design, as a module to work.
Platform: | Size: 8192 | Author: Jerd Hu | Hits:

[VHDL-FPGA-Verilog] VGA_char_ROM_success

Description: Verilog HDL语言编写的基于M4K块配置ROM的字符数据存储VGA显示实验代码，引脚分配适用于21EDA的EP2C8Q208开发板, 详细解说请参见特权同学《深入浅出玩转FPGA》视频教程中的《Lesson30：SF-EP1C开发板实验9——基于M4K块配置ROM的字符数据存储VGA显示实验》-experimental code written in Verilog HDL language，ROM configuration based on M4K block for the character data storage and VGA display, pin assignment for the EP2C8Q208 21EDA development board, for a detailed explanation you can see 《Lesson30：SF-EP1C开发板实验9——基于M4K块配置ROM的字符数据存储VGA显示实验》in the book《深入浅出玩转FPGA》.
Platform: | Size: 785408 | Author: LM | Hits:

[VHDL-FPGA-Verilog] ROM

Description: 本代码实现的是生成随机数的verilog 代码。可在ModelSim中仿真-The code is the verilog code to generate random numbers. In the simulation in the ModelSim
Platform: | Size: 1024 | Author: kmao | Hits:

[VHDL-FPGA-Verilog] rom

Description: verilog 编写的rom代码，开发环境为quartus-rom write verilog code development environment for quartus
Platform: | Size: 97280 | Author: li | Hits:

[VHDL-FPGA-Verilog] VGA_ROMCHAR

Description: verilog源代码，实现将字符数据存储到rom里面，在输出到vga显示，适用vertex5-verilog source code to achieve the character data stored in the rom inside, in the output to vga display for vertex5
Platform: | Size: 1897472 | Author: flier | Hits:

[VHDL-FPGA-Verilog] rom_verilog

Description: verilog 源代码，非常简单的一种ROM的可综合的写法，适合新手学习之用。-verilog source code，simply implementation of ROM with synthesisable coding-sytle， special for the beginners.
Platform: | Size: 1024 | Author: 李海华 | Hits:

[VHDL-FPGA-Verilog] RTL

Description: verilog编写的关于使用MENTOR的MBISTArchitect进行momery的自测试代码，包含测试算法模型，SRAM,ROM模型-verilog prepared by the use of MBISTArchitect for momery MENTOR self-test code, including test algorithm model, SRAM, ROM model
Platform: | Size: 305152 | Author: | Hits:

[Other] Verilog-135-classic-design

Description: verilog的135个经典设计，适合初学者自学。内有FIR、数字钟、交通灯、串转并、ram、rom等等常用模块的完整verilog代码，以及测试程序。还有基本的设计源码-verilog of 135 classic design, suitable for beginners learning. There are FIR, complete verilog code for a digital clock, traffic lights, and turn string, ram, rom, etc. commonly used modules, and test procedures. There are basic design source
Platform: | Size: 116736 | Author: 王凌 | Hits:

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