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[VHDL-FPGA-Verilog] Lab20

Description: the booth algorithm to implement the 32bits multiplication.-the booth algorithm to implement the 32bit 's multiplication.
Platform: | Size: 56320 | Author: 王琪 | Hits:

[Algorithm] GF_binomial

Description: 為一個可處理多項式乘法的verilog code-Treatment for a polynomial multiplication verilog code
Platform: | Size: 3072 | Author: hitecc | Hits:

[VHDL-FPGA-Verilog] mutip

Description: 16位乘法器 16位乘法器 -16-bit multiplier 16 multiplier 16 multiplier
Platform: | Size: 1024 | Author: | Hits:

[MPI] floatmul

Description: 采用VERILOG 语言进行设计 实现32位浮点数乘法运算 结果已经验证过 放心使用-Verilog design language used to achieve 32-bit floating-point multiplication results have been verified ease of use
Platform: | Size: 1024 | Author: NOVEI | Hits:

[VHDL-FPGA-Verilog] sin.tar

Description: 神奇的sin波生成verilog源码，非常简单的代码无需乘法即可生成sin,cos，值得搞算法的人借鉴-Magic sin wave generated Verilog source code, the code is very simple multiplication can be generated without sin, cos, worthy people from engaging in algorithm
Platform: | Size: 2048 | Author: yangyu | Hits:

[Documents] chengfa

Description: 实现乘法功能，用verilog语言可以编译的乘法程序源代码-The realization of multiplication functions, verilog language can be used to compile the source code of the multiplication process
Platform: | Size: 335872 | Author: wangjing | Hits:

[VHDL-FPGA-Verilog] santhosh_multiplier

Description: This has verilog code for multiplication.. It will be useful for beginners of verilog.. The testbench for multiplier is also attached with the file setup. Comments are welcome
Platform: | Size: 9216 | Author: santhosh | Hits:

[VHDL-FPGA-Verilog] cpu(FinalWithYS)

Description: verilog实现的八位CPU，包括乘法、除法以及多种寻址方式。代码中包括测试模块，可以直接在试验箱上运行。-verilog to achieve the eight CPU, including multiplication, division, as well as addressing a variety of ways. Code, including test modules, can be run directly in the chamber.
Platform: | Size: 8192 | Author: 鲁迪 | Hits:

[VHDL-FPGA-Verilog] modifiedBoothMultiplier

Description: verilog code for modified booth multiplication using maxplus2
Platform: | Size: 1024 | Author: ehsan | Hits:

[VHDL-FPGA-Verilog] FastCplxMuply

Description: This zip folder contains the verilog code for fast complex multiplication source code and its test bench
Platform: | Size: 1024 | Author: Jaganathan | Hits:

[source in ebook] 63535312DCTofJPEG

Description: 用verilog代码实现JPEG压缩编码过程中的DCT模块，用移位加法实现了乘法-Verilog code using JPEG compression encoding process to achieve the DCT module, with the shift to achieve the multiplication addition
Platform: | Size: 2048 | Author: jiang | Hits:

[VHDL-FPGA-Verilog] mix

Description: 本代码是基于Verilog语言，是在伽罗瓦域GF(2^8)上完成加法和乘法运算，主要完成ASE加密的列混合运算-This code is based on the Verilog language, is the Galois field GF (2 ^ 8) on the completion of addition and multiplication, the main column of the completion of ASE encryption hybrid operation
Platform: | Size: 230400 | Author: 钟佳荣 | Hits:

[VHDL-FPGA-Verilog] 8-by-8-Multiplier

Description: 8x8 bit multiplication verilog code
Platform: | Size: 50176 | Author: praveen | Hits:

[VHDL-FPGA-Verilog] module000798

Description: 16x16 bit multiplication verilog code
Platform: | Size: 47104 | Author: praveen | Hits:

[VHDL-FPGA-Verilog] Multiplier16

Description: 本文设计了一种可以实现16位有符号/无符号二进制数乘法的乘法器。该乘法器采用了补码一位乘（Booth算法), 简化了部分积的数目, 减少了某些加法运算,从而提高了运算速度。该乘法器利用Verilog代码实现，通过Modelsim软件对相应的波形进行仿真验证，并通过QuartusII软件对源码进行编译综合。-This paper designed a 16 signed/unsigned binary number multiplication of the multiplier can be achieved. The multiplier complement a multiply (Booth algorithm), simplifying the number of partial product, reducing some of the addition operation, thereby improving the operation speed. The multiplier Verilog code through Modelsim software on the corresponding waveform simulation, source code compile comprehensive and through QuartusII software.
Platform: | Size: 5754880 | Author: hxy | Hits:

[VHDL-FPGA-Verilog] add_tree

Description: 加法树的源代码，是乘法和除法的基础，也即数字电路的verilog基础代码，已经仿真过，完全正确-Adder tree source code, multiplication and division, digital circuit verilog code base simulation entirely correct
Platform: | Size: 39936 | Author: 冷先生 | Hits:

[Other] Low-Error-and-Hardware-Efficient-Fixed-Width-Mult

Description: VERILOG Code for IEEE Paper Low-Error and Hardware-Efficient Fixed-Width Multiplier by Using the Dual-Group Minor Input Correction Vector to Lower Input Correction Vector Compensation Error Run by ModelSim 6.2 software Here paper output and modified paper output can be provided. Phase-1 folder consists of paper output High speed msb multiplication. In phase-2 folder consists of slight change before the multiplication process check the if the multiplication result will give msb or not , if it s possible continue multiplication process otherwise zero can be put on the result.
Platform: | Size: 783360 | Author: anandg | Hits:

[VHDL-FPGA-Verilog] ParallelSerialMult

Description: 用verilog代码实现了 并行线性序列乘法器，流水线技术实现了乘法操作-Verilog code using a linear sequence of parallel multipliers, pipeline technology to achieve a multiplication operation
Platform: | Size: 2048 | Author: 蒋帅 | Hits:

[Software Engineering] verilog-code-for-8bit-multiplier-using-vedic-algo

Description: The vedic multiplier is used perform 16 bit multiplication using urdhva tiryakbhyam sutra. this produces the results with high speed and utilizes low power which is most efficient for the real time processors.
Platform: | Size: 11264 | Author: naz | Hits:

[VHDL-FPGA-Verilog] half_band

Description: 半带滤波器verilog源代码，主要用于采样率变换系统中，采用乘法积累加器，很好的例子，供大家参考-Half band filter verilog code, mainly for the sampling rate conversion system, use the multiplication accumulation adder, a good example, for your reference
Platform: | Size: 1024 | Author: 张俊 | Hits:
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