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[VHDL-FPGA-Verilog] 数字频率计实验报告 DL : 1: 课程设计要求设计并用FPGA实现一个数字频率计，具体设计要求如下：测量频率范围： 10Hz～100KHz 精度： ΔF / F ≤ ±2 % 系统外部时钟： 1024Hz 测量波形：方波 Vp-p ＝ 3～5 V 硬件设备：Altera Flex10K10 五位数码管 LED发光二极管编程语言：Verilog HDL / VHDL-curriculum design and FPGA design to achieve a digital frequency meter, the specific design requirements are as follows : measurement frequency range : 10Hz to 100KHz precision : F/F 2% external clock system : 1024Hz Waveform Measurement : square Vp-p = 3 ~ 5 V hardware : Altera Flex10K10 five digital LED light emitting diode programming languages : Verilog HDL/VHDL
Update : 2025-02-17 Size : 141kb Publisher : 兰
[VHDL-FPGA-Verilog] ModelSim6c_SE_Cracker DL : 0: crack for ModelSim, a Verilog, VHDL and mixed VHDL / Verilog CAD simulator for FPGA, board and IC design.-crack for ModelSim, a Verilog. VHDL and mixed VHDL/Verilog simulator for CAD F PGA, board and IC design.
Update : 2025-02-17 Size : 286kb Publisher : 陈亨利
[VHDL-FPGA-Verilog] FIR_verilog DL : 0: 基于verilog的FIR滤波器，有两种实现方法，分别给出仿真波形-Verilog based on the FIR filter, there are two methods, respectively, the simulation waveform
Update : 2025-02-17 Size : 614kb Publisher : yejianchao
[VHDL-FPGA-Verilog] fsk DL : 0: Update : 2025-02-17 Size : 200kb Publisher : 汪芸
[VHDL-FPGA-Verilog] alu DL : 0: 4bit ALU（运算逻辑单元）的设计给出了此次设计alu的输入输出结构及相应的位数。其中C0是一位的进位输入，A和B分别是4位的数据输入，S0、S1、M分别为一位的功能选择输入信号；Cout是一位的进位输出，F是4为的运算结果输出。-4bit ALU (arithmetic logic unit) design is given in the design of alu input and output structure and the corresponding median. C0 which is a binary input of, A and B are four data entry, S0, S1, M, respectively, as a function of choice of the input signal Cout of a binary output, F is 4 for computing the results of output.
Update : 2025-02-17 Size : 1kb Publisher : chenyi
[VHDL-FPGA-Verilog] 16_FIR DL : 1: 16阶FIR滤波器--本设计用VERILOG HDL语言串行DA算法实现16阶有限频率响应滤波器！-16-order FIR filter- this design language VERILOG HDL serial DA algorithm limited frequency response of 16-order filter!
Update : 2025-02-17 Size : 781kb Publisher : yuming
[VHDL-FPGA-Verilog] Verilog_for_study DL : 0: Verilog黄金参考指南，硬件学习必备的知识！-Verilog Golden Reference Guide, hardware learning essential knowledge!
Update : 2025-02-17 Size : 458kb Publisher : way
[Algorithm] aa DL : 0: BFGS算法本程序适用于求解形如f(x)=1/2*x Ax+bx+c二次函数的稳定点-BFGS algorithm for solving This procedure applies to the form f (x) = 1/2* x Ax+ Bx+ C quadratic function of the stable point
Update : 2025-02-17 Size : 6kb Publisher : sdafad
[VHDL-FPGA-Verilog] fft_verilog DL : 0: FFT IP core 源码状态控制机-FFT IP core
Update : 2025-02-17 Size : 7kb Publisher : chris
[VHDL-FPGA-Verilog] FFT_16 DL : 0: FFT快速傅立叶变换-verilog，基于verilog的FFT源码，QuartusII上仿真通过-FFT Fast Fourier Transform-verilog, the FFT-based verilog source, QuartusII through the simulation
Update : 2025-02-17 Size : 724kb Publisher : fisher
[VHDL-FPGA-Verilog] altera_fft DL : 0: alter官方fft程序使用verilog编写需要的同学可以下载-alter the official fft program uses verilog prepared students in need can be downloaded
Update : 2025-02-17 Size : 966kb Publisher : 廖国杰
[VHDL-FPGA-Verilog] 74HC164 DL : 0: 单片机与74HC164数码管显示应用，0~F的自动显示功能-74HC164 microcontroller and digital control applications, 0 ~ F automatic display
Update : 2025-02-17 Size : 40kb Publisher :
[VHDL-FPGA-Verilog] fft DL : 0: Quartusii的FFT,使用Verilog HDL 语言的FFT-FFT based on Quartusii
Update : 2025-02-17 Size : 6.2mb Publisher : 孙兰
[VHDL-FPGA-Verilog] NET2 DL : 0: This file with the wavelet transf Mallat implementation of wavelet Verilog hdl code modules for radi Modelsim 6.6 crack, can be used f A written using Verilog DDR2 cont Simple CPU VHDL implementation an Dual-port RAM design, using Veril Verilog language, a hardware-base FPGA embedded project combat, Man Application FPGA, FPGA-chip hardw Mallat implementation of wavelet Layer of one-dimensional wavelet
Update : 2025-02-17 Size : 1.77mb Publisher : sansfroid
[VHDL-FPGA-Verilog] Matriz-F DL : 0: Verilog VGA 640x480, Matriz VGA, decoRGB
Update : 2025-02-17 Size : 428kb Publisher : ivan
[VHDL-FPGA-Verilog] 86verilog DL : 0: 以FPGA 芯片为平台构建了数字信号滤波实时处理模块, 给出了 50Hz 陷波器的切比雪夫Ê 型 IIR 数字滤波器 4 阶级联的结构, 提出了对滤波器系数量化的逼近方法, 完成了基于 FPGA 的陷波器实现, 并成功地实现了对含有工频 50Hz 噪声干扰的心电信号的滤波处理, 通过与M at lab 计算所得到的滤波处理效果进行比较分析, 结果表明: 基于FPGA 采用切比雪夫Ê 型 4 级级联结构的 IIR 数字滤波器的误差满足设计要求-　W ith the development of the techno logy of VL S I, the techno logy fo r digital signal p rocessing has developed rap idly . In th is paper, the arch itecture of 50Hz four th2 o rder Chebyshev′ s ModelÊ digital f ilter is show n . In the same t i me, themethod fo r f ilter coeff icient quant if icat i on is p resented . How ever, the f ilter based on FPGA is i mp lemented . The f ilter can p rocess digital signal successfully and its perfo rmance sat isf ies w ith design requirement .
Update : 2025-02-17 Size : 15kb Publisher : 任伟
[assembly language] UART_RS232(verilog) DL : 0: /本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值是0x145，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通信同步.程序的工作过程是：串口处于全双工工作状态，按动key2，FPGA/CPLD向PC发送“21 EDA"KEY1是复位按键。字符串（串口调试工具设成按ASCII码接受方式）；PC可随时向FPGA/CPLD发送0-F的十六进制数据，FPGA接受后显示在7段数码管上。-/ This module function is to verify that the basic serial communication functions and PC. A serial debugging tools to verify the functionality of the program needs to be installed on the PC. Implementation of a transceiver a 10 bit (ie no parity bit) serial controller, 10 bit is a start bit, 8 data bits, 1 stop bit. Serial port baud rate law decided the procedures defined div_par parameters, the baud rate can change the parameters. The procedures set div_par the value is 0x145, corresponding to the baud rate is 9600. Eight times the baud rate clock to send or accept every bit of the cycle time is divided into eight time slots so that the communication synchronization. Program of work process: the serial port in full-duplex state, pressing key2 the FPGA/CPLD sent to the PC " 21 EDA" KEY1 reset button. Hexadecimal data string (serial debugging tool set to accept the way the ASCII code) 0-F PC may at any time be sent to the FPGA/CPLD, FPGA accepted displayed on the 7-segment LED
Update : 2025-02-17 Size : 586kb Publisher : 饕餮小宇
[VHDL-FPGA-Verilog] traffic DL : 0: 交通灯设计，用verilog语言来实行，不包含设计原理图(aknsh s kjsf kwfh jfls ljfsl s lfjls jlsj ls jlf l ljfs ljljl f jljl ljjlsfj ljlsfj ljsflhig)
Update : 2025-02-17 Size : 21kb Publisher : 自渎
[VHDL-FPGA-Verilog] HDL_equation DL : 0: Verilog Program to implement the function f=x+yz and Testbench for all the possible inputs using For Loop
Update : 2025-02-17 Size : 5kb Publisher : liki20
[VHDL-FPGA-Verilog] Verilog HDL DL : 0: 2015年全国电子设计大赛F题，时间间隔测量模块，占空比测量模块，ISE编写的verilog程序。(2015 national electronic design competition F title, time interval measurement module, verilog program written by ISE.)
Update : 2025-02-17 Size : 2kb Publisher : 鹤鹤鹤鹤

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