Description: 一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.两种方式,包含testbench Platform: |
Size: 2279 |
Author:彭帅 |
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Description: 这是从opencores下的fifo代码,包括了异步和同步的,还有写的testbench,希望对大家有用.-This is opencores fifo under the code, including asynchronous and synchronous. There testbench written in the hope that useful for all. Platform: |
Size: 20480 |
Author:daiowen |
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Description: 一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.两种方式,包含testbench-Verilog language describes a synchronous fifo, including: Fifo using declared registers for storage and Fifo using (model of) standard memory chip for storage. In two ways, including Testbench Platform: |
Size: 2048 |
Author:彭帅 |
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Description: Example of a FIFO code in verilog language, to control a bus. With a memory stack and a testbench. Platform: |
Size: 846848 |
Author:Lokous |
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Description: 异步fifo,用Verilog编写,包含testbench,已经通过modelsim调试,内含文档和波形图-Asynchronous fifo, to prepare to use Verilog, including testbench, debug modelsim has passed, including documents and wave Platform: |
Size: 40960 |
Author:iechshy1985 |
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Description: 异步fifo,用Verilog编写,包含testbench,已经通过调试,需要的下载-Asynchronous fifo, to prepare to use Verilog, including testbench, debugging has been passed, the need to download Platform: |
Size: 25600 |
Author:iechshy1985 |
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Description: 用verilog写的输出数据宽度可变的FIFO,输入数据为32-bit,输出数据可以配置为4-1任意bit。有设计文件和testbench-Use verilog to write a variable width of the output data FIFO, input data for the 32-bit, output data can be configured as 4-1 arbitrary bit. There are design files and testbench Platform: |
Size: 5120 |
Author:keven |
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Description: 同步与异步FIFO的verilog实现,包括源代码,testbench,测试以及综合通过,还有相关参考资料-Synchronous and asynchronous FIFO verilog achieve, including source code, testbench, test and integrated through, as well as related references Platform: |
Size: 1715200 |
Author:gt |
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Description: 16位FIFO的硬件电路,使用verilog实现。文件内含组合逻辑和寄存逻辑两种方法的实现,以及对应的testbench测试代码-16 FIFO hardware circuits using verilog implementation. File contains a combination of logic and storage logic to achieve the two methods, and the corresponding testbench test code Platform: |
Size: 33792 |
Author:chenhaoc |
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