Description: 该工程是基于verilog hdl 语言编写的帧传输协议HDLC帧的发送端代码，会用QUATUSII的人都应该知道如何使用，希望能给你带来帮助-The project is based on the language verilog hdl frame transmission protocol HDLC frame of this generation - Codes will be used QUATUSII people should know how to use, in the hope of giving you helpful Platform: |
Size: 382986 |
Author:何丹萍 |
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Description: 该工程是基于verilog hdl 语言编写的帧传输协议HDLC帧的发送端代码，会用QUATUSII的人都应该知道如何使用，希望能给你带来帮助-The project is based on the language verilog hdl frame transmission protocol HDLC frame of this generation- Codes will be used QUATUSII people should know how to use, in the hope of giving you helpful Platform: |
Size: 382976 |
Author:何丹萍 |
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Description: 基于Verilog语言的数字通信系统的帧同步的实现原理以及Verilog代码实现-Verilog language-based digital communications system, the realization of the principle of frame synchronization as well as the Verilog code Platform: |
Size: 481280 |
Author:黄虎 |
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Description: RFID系统的IEEE的文章，安全协议，认证-
In this paper, we first propose a cryptographic
authentication protocol which meets the privacy
protection for tag bearers, and then a digital Codec for
RFID tag is designed based on the protocol. The
protocol which uses cryptographic hash algorithm is
based on a three-way challenge response
authentication scheme.
In addition, we will show how the three different
types of protocol frame formats are formed by
extending the ISO/IEC 18000-3 standard[3] for
implementing the proposed authentication protocol in
RFID system environment. The system has been
described in Verilog HDL and also synthesized using
Synopsys Design Compiler with Hynix 0.25 µ m
standard-cell library. From implementation results, we
found that the proposed scheme is well suite to
implement robust RFID system against active attacks
such as the man-in-the-middle attack. Platform: |
Size: 233472 |
Author:fxy |
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Description: ofdm系统中的完整帧同步模块，基于verilog实现。-ofdm system full frame synchronization module, based on verilog implementation. Platform: |
Size: 571392 |
Author:罗云 |
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Description: 一个基于verilog的数码相框的实现,全是verilog写的,里面包括一个sd驱动的文件系统-Verilog-based implementation of digital photo frame, all written in verilog, which includes a file system driver sd Platform: |
Size: 10806272 |
Author:jibaozhang |
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Description: 基于FPGA中OFDM中的帧检测，由于采用简化算法，采用较少的复数乘法器，易于硬件实现，且节省资源，采用verilog实现.-Frame detection based on FPGA for OFDM, a simplified algorithm, using less complex multiplier, easily implemented in hardware, and save resources, the SNR performance is slightly lower than the previous algorithm, but very practical. Platform: |
Size: 320512 |
Author: |
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Description: 基于FPGA Verilog驱动线性TCD1254GFG传感器驱动程序，驱动频率2MHz，帧率333帧每秒，曝光时间调节范围0-3000us，带数据读取时序1MHz。(The driver of linear TCD1254GFG sensor is driven by Verilog based on FPGA. The driving frequency is 2MHz, the frame rate is 333 frames per second, the exposure time adjusting range is 0-3000us, and the reading time sequence is 1MHz.) Platform: |
Size: 6086656 |
Author:话说有你 |
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Search - verilog frame based