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[Other resource] magnitude

Description: Verilog HDL: Magnitude For a vector (a,b), the magnitude representation is the following: A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonometric functions of sine, cosine, magnitude, and phase using an iterative process. It is made up of a series of micro-rotations of the vector by a set of predetermined constants, which are powers of two. Using binary arithmetic, this algorithm essentially replaces multipliers with shift and add operations. In a Stratix™ device, it is possible to calculate some of these arithmetic functions directly, without having to implement the CORDIC algorithm. -Verilog HDL : For a vector magnitude (a, b), the magnitude representation is the following : A common approach to implementing thes e arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonome tric functions of sine, cosine, magn itude, and phase using an iterative process. It i 's made up of a series of micro-rotations of the v ector by a set of predetermined cons tants, which are powers of two. Using binary ar praxiology metic, this algorithm essentially replaces m ultipliers with shift and add operations. In a Stratix
Platform: | Size: 12917 | Author: 郝晋 | Hits:

[Other resource] GFEMultiplierTaps

Description: 用于生成GF(2^m)有限域中乘法器的Verilog HDL源文件的C程序
Platform: | Size: 9096 | Author: ChenQiu | Hits:

[Other resource] GFEConsMulTaps

Description: 用于生成GF(2^m)有限域中常数乘法器的Verilog HDL源文件的C程序
Platform: | Size: 8056 | Author: ChenQiu | Hits:

[Other resource] GFEInvertor

Description: 用于生成GF(2^m)有限域元素求逆器的Verilog HDL源文件的C程序
Platform: | Size: 9118 | Author: ChenQiu | Hits:

[VHDL-FPGA-Verilog] magnitude

Description: Verilog HDL: Magnitude For a vector (a,b), the magnitude representation is the following: A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonometric functions of sine, cosine, magnitude, and phase using an iterative process. It is made up of a series of micro-rotations of the vector by a set of predetermined constants, which are powers of two. Using binary arithmetic, this algorithm essentially replaces multipliers with shift and add operations. In a Stratix™ device, it is possible to calculate some of these arithmetic functions directly, without having to implement the CORDIC algorithm. -Verilog HDL : For a vector magnitude (a, b), the magnitude representation is the following : A common approach to implementing thes e arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonome tric functions of sine, cosine, magn itude, and phase using an iterative process. It i 's made up of a series of micro-rotations of the v ector by a set of predetermined cons tants, which are powers of two. Using binary ar praxiology metic, this algorithm essentially replaces m ultipliers with shift and add operations. In a Stratix
Platform: | Size: 12288 | Author: 郝晋 | Hits:

[VHDL-FPGA-Verilog] GFEMultiplierTaps

Description: 用于生成GF(2^m)有限域中乘法器的Verilog HDL源文件的C程序-Used to generate GF (2 ^ m) limited domain Multiplier Verilog HDL source file of C program
Platform: | Size: 199680 | Author: ChenQiu | Hits:

[VHDL-FPGA-Verilog] GFEConsMulTaps

Description: 用于生成GF(2^m)有限域中常数乘法器的Verilog HDL源文件的C程序-Used to generate GF (2 ^ m) limited domain constant multiplier Verilog HDL source files of C procedures
Platform: | Size: 172032 | Author: ChenQiu | Hits:

[VHDL-FPGA-Verilog] GFEInvertor

Description: 用于生成GF(2^m)有限域元素求逆器的Verilog HDL源文件的C程序-Used to generate GF (2 ^ m) finite field element inversion
Platform: | Size: 173056 | Author: ChenQiu | Hits:

[VHDL-FPGA-Verilog] VerilogHDL

Description: 《设计与验证Verilog HDL》光盘内容-err
Platform: | Size: 1003520 | Author: jzhupo | Hits:

[Software Engineering] MAC

Description: 本文首先讨论了以太网介质访问控制MAC的功能和工作过程。接着介绍了以太网MAC芯片的一种设计方案，对MAC的功能进行了逻辑划分。据此可以用Verilog HDL或VHDL来加以描述，并进一步用FPCA或ASIC来加以实现，也可做成以太网MAC核.-err
Platform: | Size: 181248 | Author: charles | Hits:

[VHDL-FPGA-Verilog] shifter

Description: 移位运算器SHIFTER 使用Verilog HDL 语言编写，其输入输出端分别与键盘/显示器LED 连接。移位运算器是时序电路，在J钟信号到来时状态产生变化， CLK 为其时钟脉冲。由S0、S1 、M 控制移位运算的功能状态，具有数据装入、数据保持、循环右移、带进位循环右移，循环左移、带进位循环左移等功能。 CLK 是时钟脉冲输入，通过键5 产生高低电平M 控制工作模式， M=l 时带进位循环移位，由键8 控制CO 为允许带进位移位输入，由键7 控制:S 控制移位模式0-3 ，由键6 控制，显示在数码管LED8 上 D[7..0]是移位数据输入，由键2 和1 控制，显示在数码管2 和1 上 QB[7..0]是移位数据输出，显示在数码管6 和5 上:cn 是移位数据输出进位，显示在数码管7 上。-SHIFTER shift calculator using Verilog HDL language, the input and output side with the keyboard/display LED connection. Shift operator is a sequential circuit, in J when the bell signals the arrival of a state of change, CLK its clock. By S0, S1, M to control the functions of the state of shift operations, with data loading, data maintenance, cycle shifted to right, into the digital cycle shifted to right, circle left, circle to the left into the digital functions. CLK is the clock pulse input through the key high 5 low M mode control, M = l-bit cyclic shift into when, controlled by the key 8 into the displacement of CO to allow input from 7 control keys: S Control Shift Mode 0-3, 6 button control from showing in the digital control LED8 on D [7 .. 0] is the shift data input from the keys 2 and 1 control, displayed in the digital tube 2 and 1 QB [7. .0] is the displacement data output, displayed on the LED 6 and 5: cn is a binary data output shift, showing 7 on in the digital co
Platform: | Size: 129024 | Author: 623902748 | Hits:

[RFID] 2

Description: RFID系统的IEEE的文章，安全协议，认证- In this paper, we first propose a cryptographic authentication protocol which meets the privacy protection for tag bearers, and then a digital Codec for RFID tag is designed based on the protocol. The protocol which uses cryptographic hash algorithm is based on a three-way challenge response authentication scheme. In addition, we will show how the three different types of protocol frame formats are formed by extending the ISO/IEC 18000-3 standard[3] for implementing the proposed authentication protocol in RFID system environment. The system has been described in Verilog HDL and also synthesized using Synopsys Design Compiler with Hynix 0.25 µ m standard-cell library. From implementation results, we found that the proposed scheme is well suite to implement robust RFID system against active attacks such as the man-in-the-middle attack.
Platform: | Size: 233472 | Author: fxy | Hits:

[VHDL-FPGA-Verilog] m_4_generater

Description: m序列发生器，verilog hdl语言 ，4位-m-sequence generator, verilog hdl language 4
Platform: | Size: 1024 | Author: 马俊汉 | Hits:

[VHDL-FPGA-Verilog] m_seq

Description: Verilog HDL 实现的4位二进制 16个m序列产生-Verilog HDL m_seq
Platform: | Size: 1944576 | Author: Joe | Hits:

[VHDL-FPGA-Verilog] M=15generator

Description: 模15序列发生器，Verilog HDL语言描述，包含文件说明和波形截图-mod15 generator, Verilog HDL language description , contains the file description and waveform capture
Platform: | Size: 17408 | Author: 孙璐 | Hits:

[ELanguage] bin_count

Description: i m sending hdl code of dm using verilog and vhdl with all blocks contain fft,ifft,scrambler,transmitter,receiver.-i m sending hdl code of ofdm using verilog and vhdl with all blocks contain fft,ifft,scrambler,transmitter,receiver.
Platform: | Size: 28672 | Author: Nilesh panchal | Hits:

[VHDL-FPGA-Verilog] buffer

Description: Hi iam Ramana a research scholar,doing my phd from sathyabama university. Title: Designa video codec h.264 processor using verilog hdl. i request you to send video codec H.264 on Verilog hdl. regards D Ramana, M.Tech(Ph.D) SATHYABAMA UNIVERSITY, CHENNAI PH:+91-9885610083
Platform: | Size: 46080 | Author: ramanna | Hits:

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