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Size: 98304 |
Author: 代数 |
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Description: IIR数字滤波器的FPGA实现(图),初学者适用-IIR digital filter realization of the FPGA (Figure), beginners applicable
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Size: 141312 |
Author: czx |
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Description: IIR code. IEEE STD 1364-1995 Verilog file: iir_par.v.
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Size: 1024 |
Author: 无名 |
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Description: 基于butterworth的iir滤波器的verilog代码,已经通过测试。-err
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Size: 10240 |
Author: 张堃 |
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Description: 对vga接口做了详细的介绍,并且有一
·三段式Verilog的IDE程序,但只有DMA
·电子密码锁,基于fpga实现,密码正
·IIR、FIR、FFT各模块程序设计例程,
·基于逻辑工具的以太网开发,基于逻
·自己写的一个测温元件(ds18b20)的
·光纤通信中的SDH数据帧解析及提取的
·VHDL Programming by Example(McGr
·这是CAN总线控制器的IP核,源码是由
·FPGA设计的SDRAM控制器,有仿真代码
·xilinx fpga 下的IDE控制器原代码,
·用verilog写的,基于查表法实现的LO
·精通verilog HDL语言编- up:in STD_LOGIC
down:in STD_LOGIC
run_stop:in STD_LOGIC
wai_t: in std_logic_vector(2 downto 0)
lift:in std_logic_vector(2 downto 0)
ladd: out std_logic_vector(1 downto 0)
)
end control
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Size: 18683904 |
Author: liuzhou |
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Description: IIR低通滤波器,matlab与verilog程序完全对应-iir low pass filter matlab result fully match the verilog output.
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Size: 101376 |
Author: 石乐 |
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Description: quartusII9.0开发环境下巴特沃斯IIR滤波器的实现完整的工程文件,同时里面有文档详细说明如何用modelsim对altera芯片进行仿真-development environment quartusII9.0 Butterworth IIR filter to achieve a complete project file, but there are documents in detail how to use modelsim to altera-chip simulation
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Size: 44793856 |
Author: 赵辉 |
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Description: 关于iir介绍,希望与大家共同提高。对于了解此滤波器的学习以及研究很有帮助,资料的详细功能-About iir introduction, hope we can together. Filter learning for understanding and study of this useful, detailed information on features
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Size: 323584 |
Author: 董军 |
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Description: verilog实现8阶的iir滤波器。对于刚学习verilog的朋友来说是一个易懂的学习资料。-verilog order to achieve the iir filter 8. For just learning verilog friend is a easy to understand learning materials.
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Size: 1024 |
Author: zh |
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Description: 2阶iir 2KHz陷波器Verilog源代码。-2-order iir 2KHz notch filter Verilog source code.
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Size: 112640 |
Author: zhouxiao |
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Description: 基于verilog HDL的IIR数字滤波器的实现-Verilog HDL-based implementation of the IIR digital filter
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Size: 4096 |
Author: |
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Description: 以FPGA 芯片为平台构建了数字信号滤波实时处理模块, 给出了 50Hz 陷波器的切比雪夫Ê 型 IIR 数字
滤波器 4 阶级联的结构, 提出了对滤波器系数量化的逼近方法, 完成了基于 FPGA 的陷波器实现, 并成功地实现了
对含有工频 50Hz 噪声干扰的心电信号的滤波处理, 通过与M at lab 计算所得到的滤波处理效果进行比较分析, 结
果表明: 基于FPGA 采用切比雪夫Ê 型 4 级级联结构的 IIR 数字滤波器的误差满足设计要求- W ith the development of the techno logy of VL S I, the techno logy fo r digital signal p rocessing has
developed rap idly . In th is paper, the arch itecture of 50Hz four th2 o rder Chebyshev′ s ModelÊ digital f ilter is
show n . In the same t i me, themethod fo r f ilter coeff icient quant if icat i on is p resented . How ever, the f ilter based on
FPGA is i mp lemented . The f ilter can p rocess digital signal successfully and its perfo rmance sat isf ies w ith design
requirement .
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Size: 15360 |
Author: 任伟 |
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Description: IIR滤波,采用Verilog编写,用于数字滤波,有测试平台,硬件测试可用-IIR filter, written using Verilog for digital filtering, a test platform
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Size: 2048 |
Author: 郭程 |
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Description: FPGA结合DSP设计,如FIR、IIR滤波器,CORDIC算法,多重采样率信号处理,FFT,有对应的VHDL/Verilog 代码code-FPGA Combines with DSP, FIR 、IIR Digital Filters,CORDIC,FFT,Adaptive Filters,VHDL/Verilog code
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Size: 10501120 |
Author: rickdecent |
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Description: 本实例利用硬件乘法器实现一个IIR滤波器。文件包含实现的verilog代码。-The example used to implement a hardware multiplier IIR filter. File contains the implementation of the verilog code.
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Size: 1081344 |
Author: 吴亮 |
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Description: 环路滤波器的FPGA实现,使用VERILOG语言,ISE13.2编译环境-The loop filter FPGA realizing, use VERILOG language, ISE13.2 compile environment
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Size: 1024 |
Author: 法克尤 |
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Description: 使用verilog语言描述的二阶巴特沃斯IIR滤波器,程序中有参数说明,已经运行通过-Using verilog language to describe the second-order Butterworth IIR filter, the program has parameter description has been run through
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Size: 1024 |
Author: jialiangquan |
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Description: Programmable IIR Filter written in Verilog and its respective modules.
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Size: 5120 |
Author: Karan |
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Description: 用Verilog实现一个IIR滤波器,并在ISE里面仿真。-Achieve an IIR filter with Verilog and simulation in ISE inside.
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Size: 1024 |
Author: Daniel |
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Description: 基于verilog hdl语言对IIR滤波器设计(Design of IIR filter based on Verilog HDL language)
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Size: 1688576 |
Author: jmcjgp
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