Search - verilog ldpc code

Search - verilog ldpc code - List

[Other] ldpc理论 DL : 0: 一篇LDPC编码的论文，具有很好的参考价值-A thiese about ldpc code, It has a good value.
Update : 2025-02-17 Size : 3.47mb Publisher : john
[SCSI-ASPI] RSverilog DL : 0: RS编码的verilog源代码，拿来和大家分享-RS-coded Verilog source code, used to share
Update : 2025-02-17 Size : 2.25mb Publisher : 刘琼
[Communication] LDPC DL : 0: ldpc码原理与应用文红电子科技大电子版全文与大家共享-Principle and Practical LDPC Code Red Electronics Science and Technology The full text of the electronic version to share with everyone
Update : 2025-02-17 Size : 12.04mb Publisher :
[Communication-Mobile] LDPC(VHDL) DL : 0: 低密度奇偶校验码的VHDL程序，用于LDPC码的硬件实现-LDPC code VHDL program for the LDPC code of hardware implementation
Update : 2025-02-17 Size : 2kb Publisher : 赵天婵
[VHDL-FPGA-Verilog] ldpc_decoder_802_3an DL : 0: 802.3an ldpc码编码、译码设计，使用VERILOG hdl语言编写，包括测试代码，-802.3an ldpc code encoding, decoding the design, use of language VERILOG hdl, including test code,
Update : 2025-02-17 Size : 770kb Publisher : 聂样
[Communication-Mobile] Stanford_ldpca_demo_software DL : 0: stanford开发的LDPCA（LDPC码的改进）的编码器和解码器，以及几个码字。-stanford development LDPCA (LDPC codes to improve) the encoder and decoder, as well as several code words.
Update : 2025-02-17 Size : 6.34mb Publisher : algernon
[Streaming Mpeg4] ldpc_encoder_802_3an.v DL : 0: LDPC 编码的Verilog源代码，我没有验证，不知道效果如何，与大家分享，供大家参考。-LDPC-coded Verilog source code, I did not verify, I do not know how to share with you, for your reference.
Update : 2025-02-17 Size : 608kb Publisher : peter
[VHDL-FPGA-Verilog] LDPC_Behavioral_VHDL DL : 0: 用VHDL语言编写的LDPC码硬件实现语言，相对于verilog的，比较简单-Using VHDL language LDPC code hardware implementation language, compared to Verilog, and relatively simple
Update : 2025-02-17 Size : 2kb Publisher : 王明
[3G develop] H_512x1024 DL : 0: LDPC 码二进制规则码生成矩阵512*1024，效果很理想-LDPC code rules binary code matrix to generate 512* 1024, the effect is very satisfactory
Update : 2025-02-17 Size : 9kb Publisher : wwwwomen
[3G develop] H_2048x4096 DL : 0: LDPC 码二进制规则码生成矩阵2048*4096，效果很理想-LDPC code rules binary code generated matrix 2048* 4096, the effect is very satisfactory
Update : 2025-02-17 Size : 55kb Publisher : wwwwomen
[Communication-Mobile] ldpc DL : 0: 最近在做毕设，ldpc码的编解码实现，这个是verilog实现。-Recently completed the set up to do, ldpc code codec implementation, this is the Verilog implementation.
Update : 2025-02-17 Size : 9kb Publisher : fly
[Communication] ldpc_c_code DL : 1: LDPC码在基于BP (Belief Propagation) 的迭代译码相结合的条件下具有逼近Shannon 限的性能，是继turbo 码后在纠错编码领域又一重大进展。压缩文件中给出了LDPC在高斯信道下的c程序。-LDPC codes based on BP (Belief Propagation) Iterative Decoding of combining conditions with performance approaching Shannon limit on the heels of turbo code error correction coding in another area of significant progress. Compressed file give the LDPC at Gaussian channel c under the procedure.
Update : 2025-02-17 Size : 7kb Publisher : aiguixia
[Communication-Mobile] ldpcverilog DL : 0: verilog编写的ldpc编码的源代码 -ldpc prepared verilog source code
Update : 2025-02-17 Size : 9kb Publisher : paul
[3G develop] decode DL : 0: LDPC的Verilog程序源代码，包括仿真数据等。文件很大，请慢慢下载-LDPC of Verilog source code, including the simulation data. Large file, please download slowly
Update : 2025-02-17 Size : 10.3mb Publisher : 陈炜炜
[VHDL-FPGA-Verilog] Realization_of_FPGA_for_LDPC_encoding DL : 0: 低密度奇偶校验码(简称LDPC码)是目前距离香农限最近的一种线性纠错码，它的直接编码运算量较大，通常具有码长的二次方复杂度．为此，利用有效的校验矩阵，来降低编码的复杂度，同时研究利用大规模集成电路实现LDPC码的编码．在ISE 8．2软件平台上采用基于FPGA的Verilog HDL语言实现了有效的编码过程，为LDPC码的硬件实现和实际应用提供了依据-Abstract：Low．density parity·check code(LDPC code)is a kind of linear eror·correcting code nearest to Shannon Limit．For LDPC cod e，the computational overhead for direct encoding operations is large，as the complexity of encod ing is the square of the length of codeword．Hence，this paper reduces the complexity of coding by using effective parity—check matrix，and realizes the encoding device for LDPC code by use of large·scale integrated circuits．The effective encoding process based on FPGA with Verilog HDL language is implemented on ISE 8．2 software platform ，providing a feasible basis for hardware implementation an d practical application of LDPC code．
Update : 2025-02-17 Size : 162kb Publisher : 秦小星
[VHDL-FPGA-Verilog] ps_decoder3_12_80_mod DL : 0: PS-LDPC码译码器的Verilog程序-PS-LDPC code decoder of the Verilog program
Update : 2025-02-17 Size : 29kb Publisher : 王昆
[VHDL-FPGA-Verilog] the-decoding-algorithm-of-ldpc DL : 0: ldpc译码算法介绍及fpga verilog系统方案设计，包括log_bp算法、min_sum算法、scaling_min_sum算法等-introducing the ldpc code decoding algorithm and the related system design，including the log_bp,the min_sum and the scaling_min_sum
Update : 2025-02-17 Size : 80kb Publisher : 类春阳
[VHDL-FPGA-Verilog] ldpc-encode DL : 0: 深空通信中AR4JA码编码的研究与实现，ＡＲ４ＪＡ码是ＬＤＰＣ码的一种，文件中是Ｖｅｒｉｌｏｇ语言的硬件实现。-Research and Implementation of the Deep Space Communications AR4JA coding, AR4JA code LDPC codes a hardware implementation of the Verilog language file.
Update : 2025-02-17 Size : 3.4mb Publisher : liangliang
[matlab] e60a9bd4-ef5c-4c89-bfb3-9da40d5e4aba DL : 0: 低密度校验码，很好用的代码，功能已经实现编码和译码(Low density parity check code, very good code, the function has been achieved encoding and decoding)
Update : 2025-02-17 Size : 8kb Publisher : RubenJH
[VHDL-FPGA-Verilog] LDPC DL : 0: LDPC编码的硬件代码,可在modelsim上验证(verilog code for ldpc encode)
Update : 2025-02-17 Size : 4.04mb Publisher : 邹润秋

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