Description: 中文名称为：硬件描述语言 Verilog（第四版）。讲解verilog HDL的经典图书。Thomas和Moorby编著，内容涵盖了:行为建模、并发进程、逻辑级建模、高级时序、逻辑综合、行为综合等方面的内容。通读此书后，不需要再读其他的verilog书籍。-Chinese name is: Hardware Description Language Verilog (Fourth Edition). Verilog HDL on classic books. Thomas and Moorby authoring, content covers: behavioral modeling, concurrent process, logic-level modeling, advanced timing, logic synthesis, behavior and other aspects of integrated content. After reading this book, do not need to read other books of Verilog. Platform: |
Size: 5331968 |
Author:王敏 |
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Description: 华为内部的FPGA设计培训教程，详细阐述了设计流程图、Verilog HDL设计、逻辑仿真、逻辑综合。对大家的学习一定有帮助的。-Huawei within the FPGA design training tutorial, a detailed flow chart of the design, Verilog HDL design, logic simulation, logic synthesis. Study of the U.S. must have help. Platform: |
Size: 34816 |
Author:张芸 |
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Description: 比特序列传送模块
把输入的八位比特数据 做循环后每个比特输出 详细请看英文描述-• To create Verilog-HDL modules written in the RTL style appropriate for both simulation and synthesis, for the various component parts of an Asynchronous Serial Data Transmitter.
• To verify the correct behaviour of each component part by means of simulation.
• To construct a top-level module corresponding to the Asynchronous Serial Data Transmitter, making use of the component parts developed above, and any additional behavioural elements which may be required.
• To verify the correct operation of the top-level design by means of simulation using a Verilog-HDL test-fixture.
• To automatically create a hierarchical logic diagram for the Asynchronous Serial Data Transmitter, generated using a Logic Synthesis tool. Platform: |
Size: 2048 |
Author:吴德昊 |
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Description: RTL 异步数据传送模块
用verilog HDL 语言描述
输入为八比特数据，执行操作后异步每比特输出。-• To create Verilog-HDL module written in the RTL style appropriate for both simulation and synthesis, for an Asynchronous Serial Data Transmitter.
• To verify the correct behaviour of the transmitter by means of simulation using a Verilog test-module.
• To automatically create a logic diagram for the Asynchronous Serial Data Transmitter, generated using a Logic Synthesis tool. Platform: |
Size: 2048 |
Author:吴德昊 |
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Description: 显示控制电路是整个场序彩色显示【15】【16】系统的心设计部分,本文采用Verilog HDL来设计。首先编写对各单元电路进行以行为级描述的Verilog代码,再用EDA工具对Verilog HDL代码进行功能仿真和逻辑综合。-Display control circuit is the field sequential color display 【15】 【16】 system design part of the heart, this paper Verilog HDL to design. First of all write circuits of each unit described in behavioral Verilog code, and then EDA tools on the Verilog HDL code for functional simulation and logic synthesis. Platform: |
Size: 4121600 |
Author:王朔 |
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Description: 用design compiler对verilog hdl的程序进行逻辑综合最后生成门级网表即用门生成的电路图。-Verilog hdl with design compiler of the logic synthesis procedure generates the final gate-level netlist that is generated with the door circuit. Platform: |
Size: 681984 |
Author:康华 |
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Description: Verilog HDL 数字设计与综合，夏宇闻译。本书重点关注如何应用verilog语言进行数字电路和系统的设计和验证，不仅讲解语法，更从基本概念讲起，逐渐过渡到编程语言接口以及逻辑综合等高级主题。-The design and synthesis of Verilog HDL digital, Xia Wen translation. The book focused on how to apply the verilog language for the design and verification of digital circuits and systems, not only explain the grammar, the more I start from the basic concept, and a gradual transition to advanced topics such as programming language interface and logic synthesis. Platform: |
Size: 12174336 |
Author:huluobo |
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Description: 以硬件描述语言（Verilog或VHDL）所完成的电路设计，可以经过简
单的综合与布局，快速的烧录至 FPGA 上进行测试，是现代 IC设计验证的技术主流。这些可编辑元件可以被用来实现一些基本的逻辑门电路（比如AND、OR、XOR、NOT）或者更复杂一些的组合功能比如解码器或数学方程式。在大多数的FPGA里面，这些可编辑的元件里也包含记忆元件例如触发器（Flip－flop）或者其他更加完整的记忆块。-A hardware description language (Verilog or VHDL) the completed circuit design, synthesis and layout through a simple and fast burn to the FPGA for testing, is the modern mainstream IC design verification techniques. These editable element can be used to implement some basic logic gates (such as AND, OR, XOR, NOT), or a combination of more complex functions such as decoders or mathematical equations. In most of the FPGA inside, these elements can be edited in memory elements such as flip-flops also includes (Flip-flop), or other more complete memory block. Platform: |
Size: 221184 |
Author:田海 |
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Description: 首先要知道自己在干什么？数字电路(fpga/asic)设计就是逻辑电路的实现，这样子说太窄了，因为asic还有不少是模拟的，呵呵。我们这里只讨论数字电路设计。实际上就是如何把我们从课堂上学到的逻辑电路使用原理图(很少有人用这个拉)，或者硬件描述语言(Verilog/VHDL)来实现，或许你觉得这太简单了，其实再复杂的设计也就是用逻辑门电路搭起来的。你学习逻辑电路的时候或许会为卡拉图，触发器状态推倒公式而感到迷惑，但是其实有一点可以放心的是，实际设计中只要求你懂得接口时序和功能就可以了，用不着那么复杂得推倒公式，只要你能够用语言把逻辑关系表述清楚就可以了，具体这个逻辑关系采用什么门电路搭的，可以不关心，综合工具(synthesis tool)可以帮你处理。当然你要知道基本门电路的功能，比如D触发器，与门，非门，或门等的功能(不说多的，两输入的还是比较简单的)。-First of all to know what you are doing? Digital circuit (fpga/asic) design is the realization of the logic circuit, so that is too narrow, because there are a lot of asic simulation, huh, huh. We only discuss digital circuit design here. Is actually how we use the logic the classroom to use the schematic diagram (very few people use this pull), or hardware description language (Verilog/VHDL) to achieve, perhaps you think this is too simple, in fact, complex design That is, with the logic gate to build up. When you learn the logic of the circuit may be for the Karata, flip-flop state of the formula and feel confused, but in fact there is one thing can be assured that the actual design only requires you to understand the interface timing and function can be, and not so complicated Down the formula, as long as you can use the language to express the logical relationship can be clear, the specific logical relationship with what the door to take, you can not care, comprehensive tools (syn Platform: |
Size: 19456 |
Author:吕攀攀 |
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