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[VHDL-FPGA-Verilog] Pall_FIR

Description: FIR低通滤波器得设计，采用并行算法设计-FIR low-pass filter was designed in parallel algorithm design
Platform: | Size: 2004992 | Author: luyingc | Hits:

[VHDL-FPGA-Verilog] LowpassfilterVHDLcord

Description: 低通滤波器的VHDL代码，需要的可以下来看看，本人QQ147440013，有志同道合的人可以加我哦-Low-pass filter of the VHDL code, need to take a look at the can down, I QQ147440013, have like-minded people can add me, oh
Platform: | Size: 4096 | Author: 黄建 | Hits:

[VHDL-FPGA-Verilog] rmfilter

Description: 低通滤波器在QUARTUS7.0开发环境下的文本与框图结合的实现方法的源代码-Low-pass filter QUARTUS7.0 development environment in the text and diagram combination of methods to achieve source code
Platform: | Size: 10240 | Author: Rebecca | Hits:

[Other] 17jie_fir

Description: 采用VHDL语言实现17阶的数字低通滤波器的设计-VHDL language used to achieve 17 the number of bands of low-pass filter design
Platform: | Size: 290816 | Author: 望天 | Hits:

[matlab] LPF

Description: IIR低通滤波器，matlab与verilog程序完全对应-iir low pass filter matlab result fully match the verilog output.
Platform: | Size: 101376 | Author: 石乐 | Hits:

[VHDL-FPGA-Verilog] filter_verilog

Description: 用verilog实现的低通滤波器，输入输出精度为64位，并附有测试程序。-Use verilog to achieve a low-pass filter, input and output accuracy of 64, together with testing procedures.
Platform: | Size: 82944 | Author: 周峰 | Hits:

[DSP program] dspddc_R12p1

Description: 基于DSPbuilder搭建的DDC，里面包括CIC滤波器，FIR低通滤波器，HB半带滤波器，NCO等，实现了GC5016芯片的功能-DSPbuilder erected based on DDC, which include the CIC filter, FIR low-pass filter, HB half-band filter, NCO, etc. to achieve the function of the GC5016 chip
Platform: | Size: 17408 | Author: 郑程 | Hits:

[Books] fir

Description: 本文以软件无线电为指导，提出基于CORDIC算法利用FPGA平台数字下变频器设计方案。首先分析下变频器的结构；然后采用模块化设计思想，将数字下变 频的功能模块包括数字控制振荡器、CIC抽取滤波、HBF抽取滤波器、FIR低通滤波器进行分析和FPGA的设计；最后在 MATLAB/DSPBuilder下硬件仿真模块进行仿真并给出仿真结果。-In this paper, software-defined radio as the guidance, based on the CORDIC algorithm uses the FPGA platform, digital down-converter design. First analyzes the structure of down-converter and then use a modular design concept, the digital down-conversion function modules including digital controlled oscillator, CIC decimation filtering, HBF decimation filter, FIR low-pass filter for analysis and FPGA design the final In the MATLAB/DSPBuilder under the hardware emulation module simulation and simulation results.
Platform: | Size: 201728 | Author: jiang | Hits:

[Energy industry] Verilog

Description: 全加器的Verilog 实现代码 寄存器的Verilog 实现代码-Low-pass filter integral part of full-adder and register the Verilog implementation code
Platform: | Size: 3072 | Author: 田静 | Hits:

[Embeded Linux] 83390078DDS

Description: DDS的工作原理是以数控振荡器的方式产生频率、相位可控制的正弦波。电路一般包括基准时钟、频率累加器、相位累加器、幅度/相位转换电路、D/A转换器和低通滤波器（LPF）。频率累加器对输入信号进行累加运算，产生频率控制数据X（frequency data或相位步进量）。相位累加器由N位全加器和N位累加寄存器级联而成，对代表频率的2进制码进行累加运算，是典型的反馈电路，产生累加结果Y。幅度/相位转换电路实质上是一个波形寄存器，以供查表使用。读出的数据送入D/A转换器和低通滤波器。-DDS works the way we are digitally controlled oscillator frequency, phase controlled sine wave. Circuits generally include reference clock, frequency accumulator, phase accumulator, amplitude/phase converter circuit, D/A converter and low-pass filter (LPF). The frequency accumulator to accumulate the input signal operation to produce the frequency control data X (frequency data or phase stepping volume). From the N-bit phase accumulator and the N-bit full adder cascade accumulation register is made on behalf of the frequency of the two binary codes accumulation operation, is a typical feedback circuit, resulting in cumulative results of Y. Amplitude/phase converter circuit is essentially a waveform register for look-up table to use. Read out the data into the D/A converter and low pass filter.
Platform: | Size: 44032 | Author: 394177191 | Hits:

[Software Engineering] DDS1

Description: 直接数字频率合成器（Direct Digital synthesizer）是从相位概念出发直接合成所需波形的一种频率合成技术。一个直接数字频率合成器由相位累加器、加法器、波形存储ROM、D/A转换器和低通滤波器（LPF）构成-Direct digital frequency synthesizer (Direct Digital synthesizer) is the concept of direct synthesis from the requirements phase of a waveform synthesizer technology. A direct digital frequency synthesizer by the phase accumulator, adder, waveform storage ROM, D/A converter and low pass filter (LPF) constitute
Platform: | Size: 261120 | Author: wufeng | Hits:

[VHDL-FPGA-Verilog] VerilogFIR

Description: low pass FIR filter programmed by Verilog, you can change the coefficients in the program to achieve different response
Platform: | Size: 4225024 | Author: 吴恒 | Hits:

[VHDL-FPGA-Verilog] FIR2

Description: 以VERILOG语言描绘的用TLC549和TLC5615的数字低通滤波器的程序-VERILOG language used to describe the TLC549 and TLC5615 digital low pass filter process
Platform: | Size: 1024 | Author: 李柏睿 | Hits:

[VHDL-FPGA-Verilog] FIR_Filter

Description: verilog的32阶FIR低通滤波器描述-verilog 32-order FIR low-pass filter described
Platform: | Size: 1378304 | Author: yuanjun | Hits:

[VHDL-FPGA-Verilog] filter_lowpass

Description: 基于Verilog的低通滤波器的设计与实现-Based on the Verilog low-pass filter of design and implementation
Platform: | Size: 1024 | Author: 洪依 | Hits:

[VHDL-FPGA-Verilog] fir

Description: 基于verilog的 FIR低通滤波器的实现(Implementation of FIR low pass filter based on Verilog)
Platform: | Size: 140288 | Author: yaaaan | Hits:

[VHDL-FPGA-Verilog] DDS_display

Description: 自己写的FIR八戒低通滤波器，仅供参考(Write your own FIR eight quit low-pass filter, for reference only)
Platform: | Size: 6893568 | Author: laobi_verilog | Hits:

[Other] 基于FPGA和IP核的FIR低通滤波器

Description: 用verilog语言实现数字电路低通滤波器(Implementation of digital circuit low-pass filter using Verilog language)
Platform: | Size: 39936 | Author: 曾今的1994 | Hits:

[Windows Kernel] low pass filter

Description: low pass filter using verilog
Platform: | Size: 589 | Author: mamine2ia | Hits:

[Windows Develop] lowpass

Description: 低通滤波，参数含通带截止频率，阻带截止频率，边带区衰减DB数设置，截止区衰减DB数设置和序列x的采样频率。(Low pass filter, parameters including passband cut-off frequency, stop band cut-off frequency, sideband attenuation DB number, cut-off area attenuation DB number setting and sequence x sampling frequency.)
Platform: | Size: 1024 | Author: 邮差 | Hits:
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