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[VHDL-FPGA-Verilog] lpm_mul

Description: ８＊８的乘法器verilog源代码,经过编译仿真的，绝对真确，对初学者很有帮助-8* 8 Multiplier verilog source code, compiled simulation, absolute authenticity, helpful for beginners
Platform: | Size: 27648 | Author: 刘东辉 | Hits:

[VHDL-FPGA-Verilog] mult8x8

Description: 一个用VerilogHDL语言编写的8X8的乘法器-a Verilog HDL language used in the preparation of the multiplier 8X8
Platform: | Size: 17408 | Author: 胡东 | Hits:

[VHDL-FPGA-Verilog] verilog_multiplier

Description: verilog实现16*16位乘法器，带测试文件-verilog achieve 16* 16 multiplier, with test documents
Platform: | Size: 25600 | Author: zzm | Hits:

[Embeded-SCM Develop] verilog.HDL.examples

Description: 许多非常有用的 Verilog 实例: ADC, FIFO, ADDER, MULTIPLIER 等-many very useful Verilog examples : ADC, FIFO, ADDER, MULTIPLIER etc.
Platform: | Size: 188416 | Author: 张驰 | Hits:

[VHDL-FPGA-Verilog] multiple

Description: 介绍了几种常用的乘法器的设计，carry_save_mult，ripple_carry_mult等，压缩包中包含结构流程图，用verilogHDL语言，采用modelsim仿真验证-This paper introduces some commonly used multiplier design, carry_save_mult, ripple_carry_mult such as, compressed package that contains the structure of flow chart, using verilogHDL language, using ModelSim simulation
Platform: | Size: 266240 | Author: yaoyongshi | Hits:

[VHDL-FPGA-Verilog] 64

Description: 64位乘法器，超前进位的，大家看看，通过仿真的，verilog的-64-bit multiplier, bit-ahead, let us look at the adoption of simulation, verilog of
Platform: | Size: 37888 | Author: | Hits:

[VHDL-FPGA-Verilog] multiplier

Description: booth乘法器： 16*16有符号乘法器，Booth编码，简单阵列，Ripple Carry Adder-booth multiplier:
Platform: | Size: 3072 | Author: chenyi | Hits:

[Other] UnsignMulti

Description: ALTERA上DE2平台，verilog描述，无符号乘法器，在数码管显示结果。-ALTERA on DE2 platform, verilog description unsigned multiplier, the result will be displayed in the digital pipe.
Platform: | Size: 878592 | Author: 徐朝凯 | Hits:

[Algorithm] multiply

Description: 这是我用verilog hdl语言写的浮点乘法器,用的是基4的booth算法,对于部分积使用了5-2压缩和3-2压缩,欢迎大家指点,也欢迎大家把它改成流水线以提高速度.-This is my verilog hdl language used to write floating-point multiplier, using a Radix-4 algorithm for the booth for part of the plot using the 5-2 and 3-2 compression compression, welcomed everyone pointing, also welcomed the U.S. put it into a pipeline to improve speed.
Platform: | Size: 4096 | Author: lanty | Hits:

[VHDL-FPGA-Verilog] multi16

Description: verilog 写的两种方式的乘法器 不错!-Verilog write the multiplier in two ways good!
Platform: | Size: 7168 | Author: rayax | Hits:

[VHDL-FPGA-Verilog] multiply

Description: Verilog hdl语言 常用乘法器设计，可使用modelsim进行仿真-Verilog hdl language commonly used multiplier design, can use the ModelSim simulation
Platform: | Size: 2048 | Author: 许立宾 | Hits:

[VHDL-FPGA-Verilog] GFmultiply

Description: Verilog hdl语言 伽罗华域GF（q）乘法器设计，可使用modelsim进行仿真-Language Verilog hdl Galois field GF (q) multiplier design, can use the ModelSim simulation
Platform: | Size: 2048 | Author: 许立宾 | Hits:

[VHDL-FPGA-Verilog] multiply

Description: 由verilog编写的乘法器，通过两个文件的调用实现。由于子模块的调用使得程序简化了许多。-Prepared by the Verilog multiplier, through the realization of the two documents call. As the sub-modules to simplify the procedure call makes a lot.
Platform: | Size: 3072 | Author: 金夕 | Hits:

[VHDL-FPGA-Verilog] twice_freqencey

Description: 用Verilog直接完成倍频的算法,经过了quartus8.0的时序仿真-Verilog multiplier used directly to complete the algorithm, as a result of timing simulation quartus8.0
Platform: | Size: 231424 | Author: nikui | Hits:

[Software Engineering] booth_multiplier

Description: Booth multiplier written in verilog
Platform: | Size: 1024 | Author: Udit | Hits:

[ELanguage] 32bit

Description: multiplier and divider verilog codes
Platform: | Size: 6144 | Author: damasqas | Hits:

[VHDL-FPGA-Verilog] Mars_EP1C6F_Fundermental_demo(Verilog)

Description: FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。-FPGA development board supporting Verilog HDL code. Chips for the Mars EP1C6F. Are the basic source experiment. Including the adder, subtraction, and multiplier, such as MUX.
Platform: | Size: 1244160 | Author: chenlu | Hits:

[VHDL-FPGA-Verilog] booth

Description: 基于verilog的booth算法的乘法器-Based on the booth algorithm verilog multiplier
Platform: | Size: 1024 | Author: gyj | Hits:

[VHDL-FPGA-Verilog] verilog

Description: verilog语言例题集锦 包含加法器，乘法器，串并转换器等verilog源代码-Example Collection contains verilog language adder, multiplier, and converters, such as string verilog source code
Platform: | Size: 113664 | Author: 刘佳扬 | Hits:

[VHDL-FPGA-Verilog] Multiplier

Description: It s a design of a 4*4 multiplier based on Verilog, using Xilinx ISE.
Platform: | Size: 859136 | Author: wayne | Hits:
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