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[VHDL-FPGA-Verilog] PINPAN

Description: 乒乓游戏 ，led流水灯控制乒乓球，按键控制甲方已方操作。详细说明看readme-ping-pong game, led lights to control water table tennis, has been chosen to control keys to operate. Details see readme
Platform: | Size: 4096 | Author: 张建 | Hits:

[SCM] sgs32

Description: Verlog HDL 写得一款32路方波发生器，例子是4路可以自己加，相位可调，频率可调，占空比可调。具体参见readme.doc.此处只提供了源码包含顶层模块sgs32.v 子模块dds.v和pll设置模块altp.v及波形驱动文件-Verlog HDL write a 32 square-wave generator, for example, is able to add 4-way, phase adjustable, adjustable frequency, adjustable duty cycle. See readme.doc. Here only provide a source module that contains the top-level sub-modules sgs32.v settings dds.v and pll module altp.v and waveform-driven document
Platform: | Size: 59392 | Author: TTHR | Hits:

[VHDL-FPGA-Verilog] Micron_SDRAM_DDR2Simulation_model_Verilog

Description: DDR2 SDRAM仿真模型，适合于ModelSim下工作，请先阅读readme-DDR2 SDRAM Simulation Model which is suitable for modelsim. Please read readme file firstly.
Platform: | Size: 20480 | Author: rar | Hits:

[VHDL-FPGA-Verilog] readmemh

Description: Verilog使用readmenh()的範例-Verilog using readmenh () example
Platform: | Size: 71680 | Author: 蕭鴻森 | Hits:

[VHDL-FPGA-Verilog] sdram-control-verilog

Description: SDRAM控制器源码，内含完整的控制器verilog源代码和测试代码，超值哈。-This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1.
Platform: | Size: 991232 | Author: runxin | Hits:

[VHDL-FPGA-Verilog] 32bitcpu

Description: 用verilog写的32位CPU源码，通过汇编语言可以实现加减乘除左移右移等运算。并且通过Lookahead算法提高了运算效率，大大节省了运算时间。通过ASC流程可以模拟出其内部电路结构。代码，过程文件，readme在文件夹中-Written by 32-bit CPU verilog source code, assembly language can be achieved through the addition, subtraction and other operations right left. And through the Lookahead algorithm improve the efficiency, significant savings in computing time. ASC process can be simulated by its internal circuit. Code, process documents, readme in the folder
Platform: | Size: 13528064 | Author: 杨岩 | Hits:

[VHDL-FPGA-Verilog] VHDLshixianCPU2

Description: vhdl实现cpu用verilog写的8位CPU源码，通过汇编语言可以实现加减乘左移右移等运算。并通过ASC流程可以模拟出其内部电路结构。代码，截图，readme在文件夹中-With 8-bit CPU to write verilog source code, assembly language can be achieved through the addition, subtraction and other operations right left. ASC process through its internal circuitry to simulate the structure. Code, screenshots, readme in the folder-cpu using verilog vhdl achieve 8-bit CPU to write source code, assembly language can be achieved through the addition and subtraction and other operations by the left right. And the process can be simulated by the ASC in its internal circuit structure. Code, screenshots, readme in the folder-With 8-bit CPU to write verilog source code, assembly language can be achieved through the addition, subtraction and other operations right left. ASC process through its internal circuitry to simulate the structure. Code, screenshots, readme in the folder
Platform: | Size: 53248 | Author: 张梦 | Hits:

[VHDL-FPGA-Verilog] RISC-CPU

Description: 精简指令集 CPU 通过仿真验证正确 (使用之前务必看readme文件，和结构图!) 1. 此cpu是夏宇闻 verilog数字系统设计教程中最后一章的例程。 2. 学习时务必先搞明白框图原理，和数据流动！！！ 3. 牢记主状态机中一条指令周期中传输的16bit=3bit指令+13bit地址。 4. 理解数据总线，和地址总线。区分数据和地址。 5. 仔细调试，因为书中有很多小错误。 程序经过quartusii编译通过，另外经过modelsim仿真正确。-RISC CPU properly verified by simulation (using the previously sure to see the readme file and structure chart!) This CPU is the last chapter Xia Wen verilog Digital System Design Guide routine. 2 study sure to thoroughly understand block diagram of the principle, and the flow of data! ! ! Keep in mind one instruction cycle in the transmission of the main state machine the 16bit = 3bit instruction+13bit address. 4 understand the data bus and address bus. Between data and addresses. Carefully debugging, because there are many small errors in the book. The program compiled through quartusii by the addition after modelsim simulation.
Platform: | Size: 4337664 | Author: 刘栋 | Hits:

[VHDL-FPGA-Verilog] fpu_double

Description: The Verilog version of the code is in folder “fpu_double”, and the VHDL version is in folder “double_fpu”. There is a readme file in each folder, and a testbench file to simulate each core. These cores are designed to meet the IEEE 754 standard for double precision floating point arithmetic.
Platform: | Size: 244736 | Author: 丁一 | Hits:

[VHDL-FPGA-Verilog] crc_verilog_xilinx

Description: 包括下面文档： readme.txt : This file crc8_8.v : CRC-8, 8-bit data input. crc12_4.v : CRC-12, 4-bit data input. crc16_8.v : CRC-16, 8-bit data input. crc_ccit_8.v : CRC-CCIT, 8-bit data input. crc32_8.v : CRC-32, 8-bit data input. crcgen.pl : Perl script used to generate Verilog Source for CRC caluculation.(Contains the following files readme.txt : This file crc8_8.v : CRC-8, 8-bit data input. crc12_4.v : CRC-12, 4-bit data input. crc16_8.v : CRC-16, 8-bit data input. crc_ccit_8.v : CRC-CCIT, 8-bit data input. crc32_8.v : CRC-32, 8-bit data input. crcgen.pl : Perl script used to generate Verilog Source for CRC caluculation.)
Platform: | Size: 10240 | Author: chris_lj | Hits:

[VHDL-FPGA-Verilog] verilog-axi-master

Description: Verilog AXI Components Readme GitHub repository: alexforencich verilog-axi
Platform: | Size: 313344 | Author: viyefo5674 | Hits:

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