Location:
Search - verilog rs
Search list
Description: RS(Reed-Solomon)码是差错控制领域中一类重要的线性分组码,由于其出众的纠错能力,被广泛地应用于各种差错控制系统中,以满足对数据传输通道可靠性的要求。
Platform: |
Size: 927 |
Author: dafanxiaoqiao |
Hits:
Description: RS编码的源代码使用Verilog在Xinloinx平台-RS coding using the source code in Verilog Xinloinx platform
Platform: |
Size: 5120 |
Author: 王锋 |
Hits:
Description: RS RS-232 至RS RS-485 RS RS-422 智能转换器-RS RS-232 to RS RS-485 RS RS-422 Intelligent Converters
Platform: |
Size: 159744 |
Author: |
Hits:
Description: 结合XILINXCPLD所做的模拟RS232通信verilog源程序-XILINXCPLD combine the simulation RS232 communication Verilog source
Platform: |
Size: 121856 |
Author: 于飞 |
Hits:
Description: 通用异步接收器/发送器(UART)是能够编程以控制计算机到附加串行设备的接口的微芯片。详细来说,它提供给计算机RS-...还有高级的UART提供了一定数量的数据缓冲,这样计算机和串行设备数据流就可以保持同样的速度。-universal asynchronous receiver/transmitter (UART) can be programmed to control computer attached to the serial device interface microchips. Details, provide it to the computer RS-High ... UART also provide a certain number of data buffer, computer equipment and serial data stream can maintain the same speed.
Platform: |
Size: 9216 |
Author: 李志 |
Hits:
Description: 这是一个rs译码器的verilog程序运行于quatus-This is a rs decoder running on Verilog quatus
Platform: |
Size: 133120 |
Author: yuanfeng |
Hits:
Description: 各种解码译码电路模型的VerilogHDL描述-various decoder decoding circuit model of Verilog HDL description
Platform: |
Size: 2048 |
Author: nil |
Hits:
Description: 这是rs(255,223)编码的verilog源程序。里面有:encode、decode、test-bench等文件。-This is rs (255,223) verilog source coding. Inside : encode, decode, test-bench and other documents.
Platform: |
Size: 18432 |
Author: 陈 |
Hits:
Description: encode.v The encoder
syndrome.v Syndrome generator in decoder
berlekamp.v Berlekamp algorithm in decoder
chien-search.v Chien search and Forney algorithm in decoder
decode.v The top module of the decoder
inverse.v Computes multiplication inverse of an Galois field element
test-bench.v The test fixture, and some brief notes on using the modules.
data-rom.v A simple data source for testing
run For those intelligence-challenged who can t run verilog
LGPL The license
-encode.v syndrome.v Syndrome generator in decoder al berlekamp.v Berlekamp gorithm in decoder chien- search.v Chien searc h and Forney in decoder algorithm decode.v The t op module of the decoder inverse.v Computes intercommunication tiplication inverse of an element over Galois field test-bench.v The test fixture. and some brief notes on using the modules. data- rom.v A simple data source for testing run For th PNA intelligence-challenged who can not run veri The log LGPL license
Platform: |
Size: 45056 |
Author: zs8292 |
Hits:
Description: Hard-decision decoding scheme
Codeword length (n) : 31 symbols.
Message length (k) : 19 symbols.
Error correction capability (t) : 6 symbols
One symbol represents 5 bit.
Uses GF(2^5) with primitive polynomial p(x) = X^5 X^2 + 1
Generator polynomial, g(x) = a^15 a^21*X + a^6*X^2 + a^15*X^3 + a^25*X^4 + a^17*X^5 + a^18*X^6 + a^30*X^7 + a^20*X^8 + a^23*X^9 + a^27*X^10 + a^24*X^11 + X^12. Note: a = alpha, primitive element in GF(2^5) and a^i is root of g(x) for i = 19, 20, ..., 30.
Uses Verilog description with synthesizable RTL modelling.
Consists of 5 main blocks: SC (Syndrome Computation), KES (Key Equation Solver), CSEE (Chien Search and Error Evaluator), Controller and FIFO Register.
-Hard-decision decoding scheme Codeword l KV (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents five bit. Uses GF (2 ^ 5) with primitive polynomial p (x) = x ^ x ^ 5 2 1 Ge nerator polynomial. g (x) = a ^ a ^ 15* 21 ^ 6 a X* X ^ a ^ 15 2* X ^ a ^ 3 25* X ^ a ^ 4 17 5* X ^ a ^ 18 ^ 6 X* a* X 30 ^ 7 ^ a ^ 20* X ^ a ^ 23 8* X ^ a ^ 9* 27 X 10 ^ a ^ 24* 11 ^ X ^ X 12. Note : a = alpha, primitive element in GF (2 ^ 5) and a ^ i is the root of g (x) for i = 19, 20, ..., 30. Uses Verilog description with synthesizab le RTL modeling. Consists of five main blocks : SC (Syndrome Computation), KES (Key Equation Solver). CSEE (Chien Search and Error Evaluator) Controller and FIFO Register.
Platform: |
Size: 14336 |
Author: 许茹芸 |
Hits:
Description: RS(32,28) encoder and decoder VHDL-RS (32,28) encoder and decoder VHDL
Platform: |
Size: 76800 |
Author: 王文 |
Hits:
Description: 一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.两种方式,包含testbench-Verilog language describes a synchronous fifo, including: Fifo using declared registers for storage and Fifo using (model of) standard memory chip for storage. In two ways, including Testbench
Platform: |
Size: 2048 |
Author: 彭帅 |
Hits:
Description: Quartus下的RS(5,3)编码器的源程序,用Verilog语言编写。-Quartus under the RS (5,3) encoder source code, using Verilog language.
Platform: |
Size: 3072 |
Author: 桃子 |
Hits:
Description: RS编码,verilog编写,可以自定义多项式,(255,233)和(204,188)均可。-RS coding, verilog prepared, can customize the polynomial, (255,233) and (204188) may.
Platform: |
Size: 5120 |
Author: sunwind |
Hits:
Description: 这是华为使用的内部培训教程!
本文主要介绍了Verilog HDL 语言的一些基本知识,目的是使初学者能够迅速掌 HDL
设计方法,初步了解并掌握Verilog HDL语言的基本要素,能够读懂简单的设计代码并
够进行一些简单设计的Verilog HDL建模。-This is Huawei s internal training course to use! This paper mainly introduces the Verilog HDL language, some basic knowledge, the purpose is to enable beginners to quickly charge of HDL design methodology, a preliminary understanding of Verilog HDL language and mastery of the basic elements that can read a simple design code and enough to carry out some simple Verilog design HDL modeling.
Platform: |
Size: 263168 |
Author: xiaoju |
Hits:
Description: 关于verilog硬件描述语言的讲经典教程,能使初学者很好地掌握利用该语言设计源程序-On the Verilog hardware description language speakers classic tutorial that will enable beginners to grasp a very good use of the language design source
Platform: |
Size: 1601536 |
Author: yuanxiaonan |
Hits:
Description: <Verilog HDL 语言编程》
RS(204,188)译码器的设计-<Verilog HDL language programming RS (204,188) Decoder
Platform: |
Size: 11264 |
Author: 李映波 |
Hits:
Description: RS[255,223]纠错码verilog源码,包含编码和解码模块,以及testbench等。-Verilog source code for RS[255,223] encoder and decoder, with testbench included.
Platform: |
Size: 27648 |
Author: 饶进平 |
Hits:
Description: 我测试过的!Verilog HDL实现RS编码。-I' ve tested it! RS coding Verilog HDL implementation.
Platform: |
Size: 983040 |
Author: kiekie |
Hits:
Description: RS译码器的设计源程序--verilog HDL实现-Design of the RS decoder source code-- Verilog HDL
Platform: |
Size: 14336 |
Author: 王垚 |
Hits: