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[File Format] hash

Description: 主要关于hash算法的一些资料，个人觉得比较好，与大家共享-Hash algorithm is mainly concerned with some of the information, individuals feel better, and the U.S. share
Platform: | Size: 4294656 | Author: 张晓梅 | Hits:

[VHDL-FPGA-Verilog] sha-1

Description: 本算法基于leon2协处理器接口标准，内含testbench，在modelsim中仿真通过，在ise9.2中综合及后仿真通过。-The algorithm is based on the leon2 co-processor interface standard, including testbench, ModelSim simulation in the adoption, in ise9.2 integrated and adopted after the simulation.
Platform: | Size: 15360 | Author: ninghuiming | Hits:

[Crack Hack] sha256_512

Description: Verilog实现的SHA256/SHA512算法，已仿真和验证-Verilog implementation of SHA256/SHA512 algorithm, simulation and verification has been done.
Platform: | Size: 7168 | Author: 费利克斯雷 | Hits:

[Crack Hack] sha

Description: 内带3个sha1的C源码。经验证都可用。在我们项目中，已经用于验证SHA1的verilog-With three within the C source code sha1. Experience certificate are available. In our project, has been used to validate SHA1 of verilog
Platform: | Size: 14336 | Author: 左宏权 | Hits:

[Crack Hack] use_3_shoft

Description: SHA-1的verilog程序，经过优化的了，希望可以对大家有帮助-SHA-1 of the verilog program, optimized, and hope that we can help you
Platform: | Size: 1315840 | Author: 韩子瑜 | Hits:

[VHDL-FPGA-Verilog] SHA_1_V

Description: 基于FIPS 180-4标准的SHA-1算法的verilog HDL实现-FIPS 180-4 standard SHA-1 algorithm-based verilog HDL implementation
Platform: | Size: 3072 | Author: pppp | Hits:

[VHDL-FPGA-Verilog] SHA-256

Description: 基于FIPS 180-4标准的SHA-256算法的verilog HDL实现-SHA-256 algorithm based on FIPS 180-4 standard verilog HDL implementation
Platform: | Size: 4096 | Author: pppp | Hits:

[VHDL-FPGA-Verilog] sha1_v01

Description: 基于FIPS 180-4标准的SHA-1算法的verilog HDL实现，分模块分别实现-FIPS 180-4 standard SHA-1 algorithm-based verilog HDL sub-modules, respectively, to achieve
Platform: | Size: 6144 | Author: pppp | Hits:

[VHDL-FPGA-Verilog] sha1-progect

Description: Xilinx XC2VP20 FPGAs. The complete SHA-1 chip Verilog source
Platform: | Size: 23552 | Author: zoran wowa | Hits:

[VHDL-FPGA-Verilog] sha1

Description: 利用verilog语言实现了SHA-1机密算法，具体算法与加密芯片ds28e01一致。-Using Verilog to achieve the SHA-1 secret algorithm, the specific algorithm is consistent with the encryption chip ds28e01.
Platform: | Size: 3072 | Author: 谭清莉 | Hits:

[VHDL-FPGA-Verilog] DS28E01_final

Description: 基于SHA-1算法和DS28E01加密芯片的FPGA系统设计，该上传文件为整个设计的系统文件。Quarter软件编程的Verilog程序，包含仿真调试界面。-Design of FPGA system based on SHA-1 algorithm and DS28E01 encryption chip。
Platform: | Size: 6718464 | Author: 谭清莉 | Hits:

[VHDL-FPGA-Verilog] ARS_SHA_1

Description: sha-1主控制模块实现了对整个sha-1流程的控制(The SHA-1 main control module realizes the control of the whole SHA-1 process.)
Platform: | Size: 1024 | Author: anglo | Hits:

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